Example #1
0
externC void 
hal_ppc405_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
{
    cyg_uint8 req;                                                            
    cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);

    if ((dev >= CYG_PCI_MIN_DEV) && (dev < CYG_PCI_MAX_DEV)) {
        HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);         
        if (0 != req) {                                                           
#ifdef CYG_PCI_IRQ_MAP
            char pci_irq_table[][4] = CYG_PCI_IRQ_MAP;
#else
#error "Need platform defined IRQ map"
#endif
            *vec = pci_irq_table[dev-CYG_PCI_MIN_DEV][req-1];
            *valid = (*vec != -1);
        } else {                                                                    
            /* Device will not generate interrupt requests. */                      
            *valid = false;                                                        
        }                                                                           
#if defined(CYGPKG_IO_PCI_DEBUG)
        diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
#endif
    } else {
        *valid = false;  // Invalid device
    }
}
Example #2
0
externC void
_mb93091_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
{
    cyg_uint32 cfg_addr, addr, status;

    if (!_mb93091_has_vdk)
	    return;
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
    if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
        // PCI bridge
        addr = _MB93091_PCI_CONFIG + (offset << 1);
    } else {
        cfg_addr = _cfg_addr(bus, devfn, offset);
        HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
        addr = _MB93091_PCI_CONFIG_DATA;
    }
    HAL_WRITE_UINT32(addr, cfg_val);
    HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
    if (status & _MB93091_PCI_STAT_ERROR_MASK) {
        // Cycle failed - clean up and get out
        HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
    }
    HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
}
Example #3
0
static void
do_lspci(int argc, char *argv[])
{
    cyg_uint8 devfn;
    cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
    cyg_pci_device dev_info;
    int i;

    while (cyg_pci_find_next(devid, &devid)) {
        devfn = CYG_PCI_DEV_GET_DEVFN(devid);
	
	// Get the device info
	cyg_pci_get_device_info(devid, &dev_info);

	diag_printf("%d:%d:%d   ",
		    CYG_PCI_DEV_GET_BUS(devid),
		    CYG_PCI_DEV_GET_DEV(devfn),
		    CYG_PCI_DEV_GET_FN(devfn));

	diag_printf("Vendor[%04x] Device[%04x] Type[%02x] Class[%06x]\n",
		    dev_info.vendor,
		    dev_info.device,
		    dev_info.header_type,
		    (dev_info.class_rev >> 8) & 0xffffff);

	if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
	    // dump bars
	    for (i = 0; i < CYG_PCI_MAX_BAR; i++)
		if (dev_info.base_address[i])
		    diag_printf("        BAR%d: %08x\n", i, dev_info.base_address[i]);
	}
    }
}
Example #4
0
externC cyg_uint16 
_mb93091_pci_cfg_read_uint16(int bus, int devfn, int offset)
{
    cyg_uint32 cfg_addr, addr, status;
    cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;

    if (!_mb93091_has_vdk)
	    return cfg_val;
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
    if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
        // PCI bridge
        addr = _MB93091_PCI_CONFIG + ((offset << 1) ^ 0x02);
    } else {
        cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
        HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
        addr = _MB93091_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
    }
    HAL_READ_UINT16(addr, cfg_val);
    HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
    if (status & _MB93091_PCI_STAT_ERROR_MASK) {
        // Cycle failed - clean up and get out
        cfg_val = (cyg_uint16)0xFFFF;
        HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
    }
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
    HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
    return cfg_val;
}
Example #5
0
static inline cyg_uint32 *pci_config_setup(cyg_uint32 bus,
					   cyg_uint32 devfn,
					   cyg_uint32 offset)
{
    cyg_uint32 *pdata, *paddr;
    cyg_uint32 dev = CYG_PCI_DEV_GET_DEV(devfn);
    cyg_uint32 fn  = CYG_PCI_DEV_GET_FN(devfn);

    if (bus == 0) {
        paddr = (cyg_uint32 *)POCCAR_ADDR;
        pdata = (cyg_uint32 *)POCCDR_ADDR;
    } else {
        paddr = (cyg_uint32 *)SOCCAR_ADDR;
        pdata = (cyg_uint32 *)SOCCDR_ADDR;
    }

    /* Offsets must be dword-aligned */
    offset &= ~3;
	
    /* Primary or secondary bus use type 0 config */
    /* all others use type 1 config */
    if (bus == pbus_nr || bus == sbus_nr)
	*paddr = ( (1 << (dev + 16)) | (fn << 8) | offset | 0 );
    else
        *paddr = ( (bus << 16) | (dev << 11) | (fn << 8) | offset | 1 );

    orig_abort_vec = ((volatile cyg_uint32 *)0x20)[4];
    ((volatile unsigned *)0x20)[4] = (unsigned)__pci_abort_handler;
    HAL_ICACHE_SYNC();

    return pdata;
}
Example #6
0
//
// Prepare for a config cycle on the PCI bus
//
static __inline__ cyg_uint32
_cfg_sel(int bus, int devfn, int offset)
{
    cyg_uint32 cfg_addr, addr;
    cyg_uint32 bcsr;

    HAL_READ_UINT32(_CSB281_BCSR, bcsr);
    bcsr = (bcsr & ~0x07) | (1<<(CYG_PCI_DEV_GET_DEV(devfn)-CYG_PCI_MIN_DEV));
    HAL_WRITE_UINT32(_CSB281_BCSR, bcsr);
    cfg_addr = _EXT_ENABLE | 
        (bus << 16) | 
        (CYG_PCI_DEV_GET_DEV(devfn) << 11) | 
        (CYG_PCI_DEV_GET_FN(devfn) << 8) | 
        ((offset & 0xFF) << 0);
    HAL_WRITE_UINT32LE(_CSB281_PCI_CONFIG_ADDR, cfg_addr);
    addr = _CSB281_PCI_CONFIG_DATA + (offset & 0x03);
    return addr;
}
Example #7
0
void
cyg_hal_plf_pci_translate_interrupt(cyg_uint32 bus, cyg_uint32 devfn,
				    CYG_ADDRWORD *vec, cyg_bool *valid)
{
    cyg_uint8 pin;
    cyg_uint32 slot = 3 - (CYG_PCI_DEV_GET_DEV(devfn) - 18);
    
    HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, pin);
    *vec = -1;
    *valid = false;

    if (slot < IXP425_PCI_MAX_DEV && pin <= IXP425_PCI_IRQ_LINES) {
	*vec = pci_irq_table[slot][pin-1];
        *valid = true;
    }
}
Example #8
0
externC void 
_mb93091_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
{
    cyg_uint8 req;                                                            
    cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);

    if (dev == CYG_PCI_MIN_DEV) {
        // On board LAN
        *vec = CYGNUM_HAL_INTERRUPT_LAN;
        *valid = true;
    } else {
        HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);         
        if (0 != req) {                                                           
            CYG_ADDRWORD __translation[4] = {                                       
                CYGNUM_HAL_INTERRUPT_PCIINTC,   /* INTC# */                         
                CYGNUM_HAL_INTERRUPT_PCIINTB,   /* INTB# */                         
                CYGNUM_HAL_INTERRUPT_PCIINTA,   /* INTA# */                         
                CYGNUM_HAL_INTERRUPT_PCIINTD};  /* INTD# */                         
                                                                                
            /* The PCI lines from the different slots are wired like this  */       
            /* on the PCI backplane:                                       */       
            /*                pin6A     pin7B    pin7A   pin8B             */       
            /* I/O Slot 1     INTA#     INTB#    INTC#   INTD#             */       
            /* I/O Slot 2     INTD#     INTA#    INTB#   INTC#             */       
            /* I/O Slot 3     INTC#     INTD#    INTA#   INTB#             */       
            /*                                                             */       
            /* (From PCI Development Backplane, 3.2.2 Interrupts)          */       
            /*                                                             */       
            /* Devsel signals are wired to, resulting in device IDs:       */       
            /* I/O Slot 1     AD30 / dev 19      [(8+1)&3 = 1]             */       
            /* I/O Slot 2     AD29 / dev 18      [(7+1)&3 = 0]             */       
            /* I/O Slot 3     AD28 / dev 17      [(6+1)&3 = 3]             */       
                                                                                
            *vec = __translation[((req+dev)&3)];        
            *valid = true;                                                         
        } else {                                                                    
            /* Device will not generate interrupt requests. */                      
            *valid = false;                                                        
        }                                                                           
        diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
    }
}
Example #9
0
externC void 
_csb281_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
{
    cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);

    // Purely slot based
    if (dev >= CYG_PCI_MIN_DEV) {
        CYG_ADDRWORD __translation[] = {                                       
            CYGNUM_HAL_INTERRUPT_PCI0,
            CYGNUM_HAL_INTERRUPT_PCI1,
            CYGNUM_HAL_INTERRUPT_LAN
        };
        *vec = __translation[dev-CYG_PCI_MIN_DEV];
        *valid = true;
    } else {
        *valid = false;
    }
#if 0
    diag_printf("Int - dev: %d, vector: %d [%s]\n", 
                dev, *vec, *valid ? "OK" : "BAD");
#endif
}
Example #10
0
externC void
hal_ppc405_pci_init(void)
{
    static int _init = 0;
    cyg_uint8 next_bus;
    cyg_uint32 cmd_state, bridge_state;

    if (_init) return;
    _init = 1;

    // Configure PCI bridge
    HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0);
    HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0);
    HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE);
    HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001);
    HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0);    
    HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0);
    HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001);
    // Indicate that the bridge has been configured
    HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
    bridge_state |= 0x0001;
    HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
    // Setup for bus mastering
    HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                            CYG_PCI_CFG_COMMAND, cmd_state);
    cyg_pci_init();
    if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
#if defined(CYGPKG_IO_PCI_DEBUG)
        diag_printf("Configure PCI bus\n");
#endif
        HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                                 CYG_PCI_CFG_COMMAND,
                                 CYG_PCI_CFG_COMMAND_MEMORY |
                                 CYG_PCI_CFG_COMMAND_MASTER |
                                 CYG_PCI_CFG_COMMAND_PARITY |
                                 CYG_PCI_CFG_COMMAND_SERR);

        // Setup latency timer field
        HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                                CYG_PCI_CFG_LATENCY_TIMER, 32);

        // Configure PCI bus.
        next_bus = 1;
        cyg_pci_configure_bus(0, &next_bus);
    }
#if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS)
    if (1) {
        cyg_uint8 req;                                                            
        cyg_uint8 devfn;
        cyg_pci_device_id devid;
        cyg_pci_device dev_info;
        int i;

        devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
        while (cyg_pci_find_next(devid, &devid)) {
            devfn = CYG_PCI_DEV_GET_DEVFN(devid);
            cyg_pci_get_device_info(devid, &dev_info);
            HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req);         

            diag_printf("\n");
            diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid));
            diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn));
            diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn));
            diag_printf("  Vendor Id: 0x%04X", dev_info.vendor);
            diag_printf(", Device Id: 0x%04X", dev_info.device);
            diag_printf(", Command: 0x%04X", dev_info.command);
            diag_printf(", IRQ: %d\n", req);
            for (i = 0; i < dev_info.num_bars; i++) {
                diag_printf("  BAR[%d]    0x%08x /", i, dev_info.base_address[i]);
                diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
                            dev_info.base_size[i], dev_info.base_map[i]);
            }
        }
    }
#endif
}
Example #11
0
externC void
_csb281_pci_init(void)
{
    static int _init = 0;
    cyg_uint8 next_bus;
    cyg_uint32 cmd_state;

    if (_init) return;
    _init = 1;

    // Initialize PCI support
    cyg_pci_init();

    // Setup for bus mastering
    HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                            CYG_PCI_CFG_COMMAND, cmd_state);
    if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
        // Force PCI-side window to 0
        HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                                 CYG_PCI_CFG_BAR_0, 0x01);
        // Enable bus mastering from host
        HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                                 CYG_PCI_CFG_COMMAND,
                                 CYG_PCI_CFG_COMMAND_MEMORY |
                                 CYG_PCI_CFG_COMMAND_MASTER |
                                 CYG_PCI_CFG_COMMAND_PARITY |
                                 CYG_PCI_CFG_COMMAND_SERR);

        // Setup latency timer field
        HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
                                CYG_PCI_CFG_LATENCY_TIMER, 32);

        // Configure PCI bus.
        next_bus = 1;
        cyg_pci_configure_bus(0, &next_bus);
    }

    if (0){
        cyg_uint8 devfn;
        cyg_pci_device_id devid;
        cyg_pci_device dev_info;
        int i;

        devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
        while (cyg_pci_find_next(devid, &devid)) {
            devfn = CYG_PCI_DEV_GET_DEVFN(devid);
            cyg_pci_get_device_info(devid, &dev_info);

            diag_printf("\n");
            diag_printf("Bus:        %d\n", CYG_PCI_DEV_GET_BUS(devid));
            diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
            diag_printf("PCI Func  : %d\n", CYG_PCI_DEV_GET_FN(devfn));
            diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
            diag_printf("Device Id : 0x%08X\n", dev_info.device);
            for (i = 0; i < dev_info.num_bars; i++) {
                diag_printf("  BAR[%d]    0x%08x /", i, dev_info.base_address[i]);
                diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
                            dev_info.base_size[i], dev_info.base_map[i]);
            }
        }
    }

    // Configure interrupts (high level)?
    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}