/* ----------------------------------------------------------------------------
Name: ChipSetOneRegister_0367ter()
Description: Writes Value to the register specified by RegAddr
Parameters:hChip ==> handle to the chip
RegAddr ==>Address of the register
Value ==>Value to be written to register
Return Value: ST_NO_ERROR (SUCCESS)
---------------------------------------------------------------------------- */
YW_ErrorType_T ChipSetOneRegister_0367qam(TUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle,U16 RegAddr, U8 Data)
{
S32 regIndex;
if(DeviceMap)
{
regIndex = ChipGetRegisterIndex(DeviceMap,IOHandle, RegAddr);
if ((regIndex >= 0) &&(regIndex < DeviceMap->Registers))
{
DeviceMap->RegMap[regIndex].Value = Data;
ChipSetRegisters_0367qam(DeviceMap, IOHandle,RegAddr,1);
}
}
else
return YWHAL_ERROR_INVALID_HANDLE;
return DeviceMap->Error;
}
YW_ErrorType_T D0367qam_Init(TUNER_IOREG_DeviceMap_t *DeviceMap,
IOARCH_Handle_t IOHandle,
TUNER_TunerType_T TunerType)
{
U16 i, j = 1;
for (i = 1; i<= DeviceMap->Registers;i++)
{
ChipUpdateDefaultValues_0367qam(DeviceMap, IOHandle, Def367qamVal[i-1].Addr, Def367qamVal[i-1].Value, i-1);
if (i != STV0367qam_NBREGS)
{
if(Def367qamVal[i].Addr==Def367qamVal[i-1].Addr + 1)
{
j++;
}
else if (j == 1)
{
ChipSetOneRegister_0367qam(DeviceMap, IOHandle, Def367qamVal[i-1].Addr, Def367qamVal[i-1].Value);
}
else
{
ChipSetRegisters_0367qam(DeviceMap, IOHandle, Def367qamVal[i-j].Addr, j);
j = 1;
}
}
else
{
if (j == 1)
{
ChipSetOneRegister_0367qam(DeviceMap, IOHandle, Def367qamVal[i-1].Addr, Def367qamVal[i-1].Value);
}
else
{
ChipSetRegisters_0367qam(DeviceMap, IOHandle, Def367qamVal[i-j].Addr, j);
j = 1;
}
}
}
ChipSetField_0367qam(DeviceMap, IOHandle, F367qam_BERT_ON, 0); /* restart a new BER count */
ChipSetField_0367qam(DeviceMap, IOHandle, F367qam_BERT_ON, 1); /* restart a new BER count */
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_OUTFORMAT,0x00);//FE_TS_PARALLEL_PUNCT_CLOCK
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_CLK_POLARITY, 0x01); //FE_TS_RISINGEDGE_CLOCK
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_SYNC_STRIP,0X00);//STFRONTEND_TS_SYNCBYTE_ON
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_CT_NBST,0x00);//STFRONTEND_TS_PARITYBYTES_OFF
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_TS_SWAP,0x00);//STFRONTEND_TS_SWAP_OFF
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_FIFO_BYPASS,0x01);//FE_TS_SMOOTHER_DEFAULT, ?? question
/* Here we make the necessary changes to the demod's registers depending on the tuner */
if(DeviceMap != NULL)
{
/*----------------------------------------------------------------------------------------*/
switch(TunerType) //important
{
case TUNER_TUNER_SHARP5469C:
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_ANACTRL,0x0D); /* PLL bypassed and disabled */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_PLLMDIV,0x01); /* IC runs at 54MHz with a 27MHz crystal */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_PLLNDIV,0x08);
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_PLLSETUP,0x18); /* ADC clock is equal to system clock */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_ANACTRL,0x00); /* PLL enabled and used */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_ANADIGCTRL,0x0b); /* Buffer Q disabled */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_DUAL_AD12,0x04); /* ADCQ disabled */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_FSM_SNR2_HTH,0x23); /* Improves the C/N lock limit */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_IQ_QAM,0x01); /* ZIF/IF Automatic mode */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_I2CRPT,0x22); /* I2C repeater configuration, value changes with I2C master clock */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_EQU_FFE_LEAKAGE,0x63);
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_IQDEM_ADJ_EN,0x04); //lwj change 0x05 to 0x04
break;
default:
break;
}
}
return YW_NO_ERROR;
}
