void Chip_USB0_Init(void)
{
/* Set up USB PLL */
Chip_USB_PllSetup();
/* Setup USB0 base clock as clock out from USB PLL */
Chip_Clock_SetBaseClock( CLK_BASE_USB0, CLKIN_USBPLL, true, true);
/* enable USB main clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB0);
Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);
/* enable USB0 phy */
Chip_CREG_EnableUSB0Phy();
}
void Chip_USB1_Init(void)
{
/* Setup and enable the PLL */
Chip_USB_PllSetup();
/* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
chained to make a divide by 8 function. Connect the output of
divider D to the USB1 base clock. */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
/* enable USB main clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
/* enable USB1_DP and USB1_DN on chip FS phy.*/
LPC_SCU->SFSUSB = 0x12;
}
void HAL_USBInit(uint8_t corenum)
{
/* Just exit if already enabled */
if (!coreEnabled[corenum]) {
/* if other code is not enabled, the enable USB PLL */
if (!coreEnabled[1 - corenum]) {
/* Neither core is enabled, so enable USB PLL first */
Chip_Clock_EnablePLL(CGU_USB_PLL);
/* Wait for PLL lock */
while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED));
}
if (corenum == 0) {
/* For core 0, enable USB0 base clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB0);
Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);
/* Turn on the phy */
Chip_CREG_EnableUSB0Phy(true);
}
else {
/* For core 1, enable USB1 base clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
/* Turn on the phy */
Chip_CREG_EnableUSB0Phy(true);
#if defined(USB_CAN_BE_HOST)
/* enable USB1_DP and USB1_DN on chip FS phy */
if (corenum && USB_CurrentMode[corenum] == USB_MODE_Host)LPC_SCU->SFSUSB = 0x16;
#endif
#if defined(USB_CAN_BE_DEVICE)
/* enable USB1_DP and USB1_DN on chip FS phy */
if (corenum && USB_CurrentMode[corenum] == USB_MODE_Device)LPC_SCU->SFSUSB = 0x12;
#endif
LPC_USB1->PORTSC1_D |= (1 << 24);
}
coreEnabled[corenum] = true;
}
#if defined(USB_CAN_BE_DEVICE) && (!defined(USB_DEVICE_ROM_DRIVER))
/* reset the controller */
USB_REG(corenum)->USBCMD_D = USBCMD_D_Reset;
/* wait for reset to complete */
while (USB_REG(corenum)->USBCMD_D & USBCMD_D_Reset) ;
/* Program the controller to be the USB device controller */
USB_REG(corenum)->USBMODE_D = (0x2 << 0) /*| (1<<4)*//*| (1<<3)*/;
if (corenum == 0) {
/* set OTG transcever in proper state, device is present
on the port(CCS=1), port enable/disable status change(PES=1). */
LPC_USB0->OTGSC = (1 << 3) | (1 << 0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
#if (USB_FORCED_FULLSPEED)
LPC_USB0->PORTSC1_D |= (1 << 24);
#endif
}
HAL_Reset(corenum);
#endif
}