/* Basic Ethernet interface initialization */ void Chip_ENET_Init(LPC_ENET_T *pENET) { Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1); reset(pENET); /* Setup MII link divider to /102 and PHY address 1 */ Chip_ENET_SetupMII(pENET, 4, 1); /* Enhanced descriptors, burst length = 1 */ pENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1); /* Initial MAC configuration for checksum offload, full duplex, 100Mbps, disable receive own in half duplex, inter-frame gap of 64-bits */ pENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); /* Setup default filter */ pENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; /* Flush transmit FIFO */ pENET->DMA_OP_MODE = DMA_OM_FTF; /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at 64 bytes */ pENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); /* Clear all MAC interrupts */ pENET->DMA_STAT = DMA_ST_ALL; /* Enable MAC interrupts */ pENET->DMA_INT_EN = 0; }
/* Setup external memories */ STATIC void SystemSetupMemory(void) { /* Setup EMC Delays */ /* Move all clock delays together */ LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12)); /* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking) and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies less than 120MHz, a divider of 1 or 2 is ok. */ Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2); LPC_CREG->CREG6 |= (1 << 16); /* Enable EMC clock */ Chip_Clock_Enable(CLK_MX_EMC); /* Init EMC Controller -Enable-LE mode */ Chip_EMC_Init(1, 0); /* Init EMC Dynamic Controller */ Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &MT48LC4M32_config); /* Init EMC Static Controller CS0 */ Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &S29GL64N90_config); /* Enable Buffer for External Flash */ LPC_EMC->STATICCONFIG0 |= 1 << 19; }
/* Basic Ethernet interface initialization */ void Chip_ENET_Init(void) { LPC_CREG->CREG6 &= ~0x7; /* Enable ethernet clock */ Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1); /* PHY TX/RX base clock routing is setup as part of SystemInit() */ #if defined(USE_RMII) LPC_CREG->CREG6 |= 0x4; #endif /* Reset ethernet and wait for reset to complete */ Chip_RGU_TriggerReset(RGU_ETHERNET_RST); while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {} /* Reset ethernet peripheral */ Chip_ENET_Reset(); /* Setup MII link divider to /102 and PHY address 1 */ Chip_ENET_Setup_MII(4, 1); IP_ENET_Init(LPC_ETHERNET); }
/* Initialize the DAC peripheral */ void Chip_DAC_Init(LPC_DAC_T *pDAC) { /* Enable ADC clocking */ Chip_Clock_EnableOpts(CLK_APB3_DAC, true, true, 1); IP_DAC_Init(pDAC); }
/* Initialize the RIT */ void Chip_RIT_Init(LPC_RITIMER_T *pRITimer) { Chip_Clock_EnableOpts(CLK_MX_RITIMER, true, true, 1); pRITimer->COMPVAL = 0xFFFFFFFF; pRITimer->MASK = 0x00000000; pRITimer->CTRL = 0x0C; pRITimer->COUNTER = 0x00000000; }
/* Initializes the UARTx peripheral */ void Chip_UART_Init(LPC_USART_Type *UARTx) { UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx); /* Enable UART clocking. UART base clock(s) must already be enabled */ Chip_Clock_EnableOpts(Chip_UART_DetermineClk(UARTx), true, true, 1); IP_UART_Init(UARTx, UARTPort); }
/* Initialize the High speed ADC */ void Chip_HSADC_Init(LPC_HSADC_T *pHSADC) { /* Enable HSADC register clock */ Chip_Clock_EnableOpts(CLK_MX_ADCHS, true, true, 1); /* Enable HSADC sample clock */ Chip_Clock_Enable(CLK_ADCHS); /* Reset HSADC, will auto-clear */ Chip_RGU_TriggerReset(RGU_ADCHS_RST); }
void Chip_USB0_Init(void) { /* Set up USB PLL */ Chip_USB_PllSetup(); /* Setup USB0 base clock as clock out from USB PLL */ Chip_Clock_SetBaseClock( CLK_BASE_USB0, CLKIN_USBPLL, true, true); /* enable USB main clock */ Chip_Clock_EnableBaseClock(CLK_BASE_USB0); Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1); /* enable USB0 phy */ Chip_CREG_EnableUSB0Phy(); }
void Chip_USB1_Init(void) { /* Setup and enable the PLL */ Chip_USB_PllSetup(); /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are chained to make a divide by 8 function. Connect the output of divider D to the USB1 base clock. */ Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4); Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2); Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true); /* enable USB main clock */ Chip_Clock_EnableBaseClock(CLK_BASE_USB1); Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1); /* enable USB1_DP and USB1_DN on chip FS phy.*/ LPC_SCU->SFSUSB = 0x12; }
/* Initialize the ADC peripheral and the ADC setup structure to default value */ void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup) { uint8_t div; uint32_t cr = 0; uint32_t clk; Chip_Clock_EnableOpts(Chip_ADC_GetClockIndex(pADC), true, true, 1); pADC->INTEN = 0; /* Disable all interrupts */ cr |= ADC_CR_PDN; ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE; ADCSetup->bitsAccuracy = ADC_10BITS; clk = 11; ADCSetup->burstMode = false; div = getClkDiv(pADC, false, ADCSetup->adcRate, clk); cr |= ADC_CR_CLKDIV(div); cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy); pADC->CR = cr; }
/* Initialize the GPDMA */ void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA) { uint8_t i; Chip_Clock_EnableOpts(CLK_MX_DMA, true, true, 1); /* Reset all channel configuration register */ for (i = 8; i > 0; i--) { pGPDMA->CH[i - 1].CONFIG = 0; } /* Clear all DMA interrupt and error flag */ pGPDMA->INTTCCLEAR = 0xFF; pGPDMA->INTERRCLR = 0xFF; /* Reset all channels are free */ for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++) { ChannelHandlerArray[i].ChannelStatus = DISABLE; } }
/* Setup external memories */ STATIC void SystemSetupMemory(void) { /* Setup EMC Delays */ /* Move all clock delays together */ LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12)); /* Setup EMC Clock Divider for divide by 2 */ Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2); LPC_CREG->CREG6 |= (1 << 16); Chip_Clock_Enable(CLK_MX_EMC); /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */ Chip_EMC_Init(1, 0, 0); /* Init EMC Dynamic Controller */ Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config); /* Init EMC Static Controller CS2 */ Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config); /* Init EMC Static Controller CS0 */ Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config); /* Enable Buffer for External Flash */ LPC_EMC->STATICCONFIG0 |= 1 << 19; }
void HAL_USBInit(uint8_t corenum) { /* Just exit if already enabled */ if (!coreEnabled[corenum]) { /* if other code is not enabled, the enable USB PLL */ if (!coreEnabled[1 - corenum]) { /* Neither core is enabled, so enable USB PLL first */ Chip_Clock_EnablePLL(CGU_USB_PLL); /* Wait for PLL lock */ while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED)); } if (corenum == 0) { /* For core 0, enable USB0 base clock */ Chip_Clock_EnableBaseClock(CLK_BASE_USB0); Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1); /* Turn on the phy */ Chip_CREG_EnableUSB0Phy(true); } else { /* For core 1, enable USB1 base clock */ Chip_Clock_EnableBaseClock(CLK_BASE_USB1); Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1); /* Turn on the phy */ Chip_CREG_EnableUSB0Phy(true); #if defined(USB_CAN_BE_HOST) /* enable USB1_DP and USB1_DN on chip FS phy */ if (corenum && USB_CurrentMode[corenum] == USB_MODE_Host)LPC_SCU->SFSUSB = 0x16; #endif #if defined(USB_CAN_BE_DEVICE) /* enable USB1_DP and USB1_DN on chip FS phy */ if (corenum && USB_CurrentMode[corenum] == USB_MODE_Device)LPC_SCU->SFSUSB = 0x12; #endif LPC_USB1->PORTSC1_D |= (1 << 24); } coreEnabled[corenum] = true; } #if defined(USB_CAN_BE_DEVICE) && (!defined(USB_DEVICE_ROM_DRIVER)) /* reset the controller */ USB_REG(corenum)->USBCMD_D = USBCMD_D_Reset; /* wait for reset to complete */ while (USB_REG(corenum)->USBCMD_D & USBCMD_D_Reset) ; /* Program the controller to be the USB device controller */ USB_REG(corenum)->USBMODE_D = (0x2 << 0) /*| (1<<4)*//*| (1<<3)*/; if (corenum == 0) { /* set OTG transcever in proper state, device is present on the port(CCS=1), port enable/disable status change(PES=1). */ LPC_USB0->OTGSC = (1 << 3) | (1 << 0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/; #if (USB_FORCED_FULLSPEED) LPC_USB0->PORTSC1_D |= (1 << 24); #endif } HAL_Reset(corenum); #endif }
/* Initialize SCT */ void Chip_SCT_Init(LPC_SCT_T *pSCT) { Chip_Clock_EnableOpts(CLK_MX_SCT, true, true, 1); }
/* Initialize SCT */ void Chip_SCT_Init(void) { Chip_Clock_EnableOpts(CLK_MX_SCT, true, true, 1); }
/* Initialize the LCD controller */ void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_CONFIG_T *LCD_ConfigStruct) { uint32_t i, regValue, *pPal; uint32_t pcd; /* Enable LCD Clock */ Chip_Clock_EnableOpts(CLK_MX_LCD, true, true, 1); /* disable the display */ pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE; /* Setting LCD_TIMH register */ regValue = ( ((((LCD_ConfigStruct->PPL / 16) - 1) & 0x3F) << 2) | (( (LCD_ConfigStruct->HSW - 1) & 0xFF) << 8) | (( (LCD_ConfigStruct->HFP - 1) & 0xFF) << 16) | (( (LCD_ConfigStruct->HBP - 1) & 0xFF) << 24) ); pLCD->TIMH = regValue; /* Setting LCD_TIMV register */ regValue = ((((LCD_ConfigStruct->LPP - 1) & 0x3FF) << 0) | (((LCD_ConfigStruct->VSW - 1) & 0x03F) << 10) | (((LCD_ConfigStruct->VFP - 1) & 0x0FF) << 16) | (((LCD_ConfigStruct->VBP - 1) & 0x0FF) << 24) ); pLCD->TIMV = regValue; /* Generate the clock and signal polarity control word */ regValue = 0; regValue = (((LCD_ConfigStruct->ACB - 1) & 0x1F) << 6); regValue |= (LCD_ConfigStruct->IOE & 1) << 14; regValue |= (LCD_ConfigStruct->IPC & 1) << 13; regValue |= (LCD_ConfigStruct->IHS & 1) << 12; regValue |= (LCD_ConfigStruct->IVS & 1) << 11; /* Compute clocks per line based on panel type */ switch (LCD_ConfigStruct->LCD) { case LCD_MONO_4: regValue |= ((((LCD_ConfigStruct->PPL / 4) - 1) & 0x3FF) << 16); break; case LCD_MONO_8: regValue |= ((((LCD_ConfigStruct->PPL / 8) - 1) & 0x3FF) << 16); break; case LCD_CSTN: regValue |= (((((LCD_ConfigStruct->PPL * 3) / 8) - 1) & 0x3FF) << 16); break; case LCD_TFT: default: regValue |= /*1<<26 |*/ (((LCD_ConfigStruct->PPL - 1) & 0x3FF) << 16); } /* panel clock divisor */ pcd = 5;// LCD_ConfigStruct->pcd; // TODO: should be calculated from LCDDCLK pcd &= 0x3FF; regValue |= ((pcd >> 5) << 27) | ((pcd) & 0x1F); pLCD->POL = regValue; /* disable interrupts */ pLCD->INTMSK = 0; /* set bits per pixel */ regValue = LCD_ConfigStruct->BPP << 1; /* set color format RGB */ regValue |= LCD_ConfigStruct->color_format << 8; regValue |= LCD_ConfigStruct->LCD << 4; if (LCD_ConfigStruct->Dual == 1) { regValue |= 1 << 7; } pLCD->CTRL = regValue; /* clear palette */ pPal = (uint32_t *) (&(pLCD->PAL)); for (i = 0; i < 128; i++) { *pPal = 0; pPal++; } }
/* Initializes the SD/MMC controller */ void Chip_SDIF_Init(LPC_SDMMC_T *pSDMMC) { Chip_Clock_EnableOpts(CLK_MX_SDIO, true, true, 1); IP_SDMMC_Init(pSDMMC); }