void Chip_SetupIrcClocking(void)
{
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* FCCO = ((44+1) * 2 * 4MHz) / (0+1) = 360MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 44, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(2);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
void Chip_SetupXtalClocking(void)
{
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Set PLL0 Source to Crystal Oscillator */
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = ((15+1) * 2 * 12MHz) / (0+1) = 384MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 15, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
/* 384MHz / (3+1) = 96MHz */
Chip_Clock_SetCPUClockDiv(3);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
void setupClock(void) {
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Set PLL0 Source to Crystal Oscillator */
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = ((19+1) * 2 * 12MHz) / (0+1) = 480MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 19, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
/* 480MHz / (3+1) = 120MHz */
Chip_Clock_SetCPUClockDiv(3);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
Chip_SYSCTL_SetFLASHAccess(FLASHTIM_120MHZ_CPU);
}
/* common clock initialisation function
* This brings up enough clocks to allow the processor to run quickly while initialising memory.
* Other platform specific clock init can be done in init_platform() or init_host_mcu()
*/
WEAK void platform_init_system_clocks( void )
{
/* CPU clock source starts with IRC */
Chip_Clock_SetMainPllSource( SYSCTL_PLLCLKSRC_IRC );
Chip_Clock_SetCPUClockSource( SYSCTL_CCLKSRC_SYSCLK );
/* Enable main oscillator used for PLLs */
LPC_SYSCTL->SCS = SYSCTL_OSCEC;
while ( ( LPC_SYSCTL->SCS & SYSCTL_OSCSTAT ) == 0 )
{
}
/* PLL0 clock source is 12MHz oscillator, PLL1 can only be the
main oscillator */
Chip_Clock_SetMainPllSource( SYSCTL_PLLCLKSRC_MAINOSC );
/* Setup PLL0 for a 480MHz clock. It is divided by CPU Clock Divider to create CPU Clock.
Input clock rate (FIN) is main oscillator = 12MHz
FCCO is selected for PLL Output and it must be between 275 MHz to 550 MHz.
FCCO = (2 * M * FIN) / N = integer multiplier of CPU Clock (120MHz) = 480MHz
N = 1, M = 480 * 1/(2*12) = 20 */
Chip_Clock_SetupPLL( SYSCTL_MAIN_PLL, PLL_M_CONSTANT - 1, PLL_N_CONSTANT - 1 );/* Multiply by PLL_M_CONSTANT, Divide by PLL_N_CONSTANT */
/* Enable PLL0 */
Chip_Clock_EnablePLL( SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE );
/* Change the CPU Clock Divider setting for the operation with PLL0.
Divide value = (480/120) = 4 */
Chip_Clock_SetCPUClockDiv( 3 ); /* pre-minus 1 */
while ( !Chip_Clock_IsMainPLLLocked( ) )
{
}
/* Connect PLL0 */
Chip_Clock_EnablePLL( SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT );
/* Wait for PLL0 to be connected */
while ( !Chip_Clock_IsMainPLLConnected( ) )
{
}
/* Setup FLASH access to 5 clocks (120MHz clock) */
Chip_FMC_SetFLASHAccess( FLASHTIM_120MHZ_CPU );
/* Enable peripheral base clocks*/
Chip_Clock_SetPCLKDiv( SYSCTL_PCLK_SPI, SYSCTL_CLKDIV_1 );
Chip_RTC_Enable( LPC_RTC, ENABLE );
Chip_Clock_SetCLKOUTSource( SYSCTL_CLKOUTSRC_RTC, 1 );
Chip_Clock_EnableCLKOUT( );
}
/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* It is safe to switch the PLL Source to Crystal Oscillator */
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
/* Fout = FCCO / ((0+1) * 2) = 120MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(1);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
Chip_Clock_SetPCLKDiv(2);
}
void HAL_USBInit(uint8_t corenum)
{
/* Enable PLL1 for 48MHz output */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
#if defined(__LPC175X_6X__)
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLL1STS_LOCKED) == 0);
#else
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0);
#endif
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1); /* P0.29 D1+, P0.30 D1- */
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
#if defined(USB_CAN_BE_HOST)
Chip_IOCON_PinMux(LPC_IOCON, 1, 19, IOCON_MODE_INACT, IOCON_FUNC2); /* USB_Power switch */
#endif
#if defined(USB_CAN_BE_DEVICE)
Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1); /* USB_SoftConnect */
#endif
LPC_SYSCTL->PCONP |= (1UL << 31); /* USB PCLK -> enable USB Per.*/
#if defined(USB_CAN_BE_DEVICE)
LPC_USB->USBClkCtrl = 0x12; /* Dev, PortSel, AHB clock enable */
while ((LPC_USB->USBClkSt & 0x12) != 0x12) ;
HAL_Reset(corenum);
#endif
}
/* Sets up USB PLL, all needed clocks and enables USB PHY on the chip. USB pins which are
muxed to different pads are not initialized here. This routine assumes that the XTAL
OSC is enabled and running prior to this call. */
void Chip_USB_Init(void)
{
#if defined(CHIP_LPC175X_6X)
/* Setup USB PLL1 for a 48MHz clock
Input clock rate (FIN) is main oscillator = 12MHz
PLL1 Output = USBCLK = 48MHz = FIN * MSEL, so MSEL = 4.
FCCO = USBCLK = USBCLK * 2 * P. It must be between 156 MHz to 320 MHz.
so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1); /* Multiply by 4, Divide by 2 */
/* Use PLL1 output as USB Clock Source */
/* Enable PLL1 */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
/* Wait for PLL1 to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
/* Connect PLL1 */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT);
/* Wait for PLL1 to be connected */
while (!Chip_Clock_IsUSBPLLConnected()) {}
#else
/* Select XTAL as clock source for USB block and divider as 1 */
LPC_SYSCTL->USBCLKSEL = 0x1;
/* Setup USB PLL1 for a 48MHz clock
Input clock rate (FIN) is main oscillator = 12MHz
PLL output = 48MHz = FIN * MSEL, so MSEL = 4
FCCO must be between 156 MHz to 320 MHz, where FCCO = PLL output * 2 * P,
so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1);
/* Wait for USB PLL to lock */
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0) {}
/* Select PLL1/USBPLL as clock source for USB block and divider as 1 */
LPC_SYSCTL->USBCLKSEL = (SYSCTL_USBCLKSRC_USBPLL << 8) | 0x01;
#endif /* defined(CHIP_LPC175X_6X) */
/* Enable AHB clock to the USB block and USB RAM. */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
}
void HAL_USBInit(uint8_t corenum)
{
/* Enable PLL1 for 48MHz output */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0);
#if defined(__LPC175X_6X__)
//LPC_PINCON->PINSEL1 &= ~((3 << 26) | (3 << 28)); /* P0.29 D+, P0.30 D- */
//LPC_PINCON->PINSEL1 |= ((1 << 26) | (1 << 28)); /* PINSEL1 26.27, 28.29 = 01 */
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, MD_PLN, FUNC1);
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, MD_PLN, FUNC1);
#if defined(USB_CAN_BE_HOST)
LPC_PINCON->PINSEL3 &= ~(3 << 6);
LPC_PINCON->PINSEL3 |= (2 << 6);
#endif
#elif defined(__LPC177X_8X__) || defined(__LPC407X_8X__)
//LPC_IOCON->P0_29 &= ~0x07; /* P0.29 D1+, P0.30 D1- */
LPC_IOCON->p[0][29] &= ~0x07;
LPC_IOCON->p[0][30] &= ~0x07;
LPC_IOCON->p[0][29] |= 0x1;
LPC_IOCON->p[0][30] |= 0x1;
//Chip_IOCON_PinMux(LPC_IOCON, 0, 29, MD_PLN, FUNC1);
//Chip_IOCON_PinMux(LPC_IOCON, 0, 30, MD_PLN, FUNC1);
#if defined(USB_CAN_BE_DEVICE)
//LPC_IOCON->P2_9 &= ~0x07; /* USB_SoftConnect */
//LPC_IOCON->P2_9 |= 0x1;
//Chip_IOCON_PinMux(LPC_IOCON, 2, 9, MD_PLN, FUNC1);
LPC_IOCON->p[2][9] &= ~0x07; /* USB_SoftConnect */
LPC_IOCON->p[2][9] |= 0x1;
#endif
#if defined(USB_CAN_BE_HOST)
//LPC_IOCON->P1_19 &= ~0x07; /* USB_Power switch */
LPC_IOCON->p[1][19] &= ~0x07;
LPC_IOCON->p[1][19] |= 0x2;
#endif
#endif
LPC_SYSCTL->PCONP |= (1UL << 31); /* USB PCLK -> enable USB Per.*/
#if defined(USB_CAN_BE_DEVICE)
LPC_USB->USBClkCtrl = 0x12; /* Dev, PortSel, AHB clock enable */
while ((LPC_USB->USBClkSt & 0x12) != 0x12) ;
HAL_Reset(corenum);
#endif
}
static void Chip_USB_PllSetup(void)
{
/* No need to setup anything if PLL is already setup for the frequency */
if (Chip_Clock_GetClockInputHz(CLKIN_USBPLL) == usbPLLSetup.freq)
return ;
/* Setup default USB PLL state for a 480MHz output and attach */
Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
/* enable USB PLL */
Chip_Clock_EnablePLL(CGU_USB_PLL);
/* Wait for PLL lock */
while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED)) {}
}
void HAL_USBInit(uint8_t corenum)
{
/* Just exit if already enabled */
if (!coreEnabled[corenum]) {
/* if other code is not enabled, the enable USB PLL */
if (!coreEnabled[1 - corenum]) {
/* Neither core is enabled, so enable USB PLL first */
Chip_Clock_EnablePLL(CGU_USB_PLL);
/* Wait for PLL lock */
while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED));
}
if (corenum == 0) {
/* For core 0, enable USB0 base clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB0);
Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);
/* Turn on the phy */
Chip_CREG_EnableUSB0Phy(true);
}
else {
/* For core 1, enable USB1 base clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
/* Turn on the phy */
Chip_CREG_EnableUSB0Phy(true);
#if defined(USB_CAN_BE_HOST)
/* enable USB1_DP and USB1_DN on chip FS phy */
if (corenum && USB_CurrentMode[corenum] == USB_MODE_Host)LPC_SCU->SFSUSB = 0x16;
#endif
#if defined(USB_CAN_BE_DEVICE)
/* enable USB1_DP and USB1_DN on chip FS phy */
if (corenum && USB_CurrentMode[corenum] == USB_MODE_Device)LPC_SCU->SFSUSB = 0x12;
#endif
LPC_USB1->PORTSC1_D |= (1 << 24);
}
coreEnabled[corenum] = true;
}
#if defined(USB_CAN_BE_DEVICE) && (!defined(USB_DEVICE_ROM_DRIVER))
/* reset the controller */
USB_REG(corenum)->USBCMD_D = USBCMD_D_Reset;
/* wait for reset to complete */
while (USB_REG(corenum)->USBCMD_D & USBCMD_D_Reset) ;
/* Program the controller to be the USB device controller */
USB_REG(corenum)->USBMODE_D = (0x2 << 0) /*| (1<<4)*//*| (1<<3)*/;
if (corenum == 0) {
/* set OTG transcever in proper state, device is present
on the port(CCS=1), port enable/disable status change(PES=1). */
LPC_USB0->OTGSC = (1 << 3) | (1 << 0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
#if (USB_FORCED_FULLSPEED)
LPC_USB0->PORTSC1_D |= (1 << 24);
#endif
}
HAL_Reset(corenum);
#endif
}
