/** * Set IRC as source clock fo all the output clocks & power down * before going to 'Deep Sleep'/'Power Down'/'Deep Power Down' modes */ static void PMC_Pre_SleepPowerDown(void) { int i; #ifndef BOARD_NGX_XPLORER_18304330 /* SDRAM in self refresh mode only for Keil & Hitex boards */ LPC_EMC->DYNAMICCONTROL |= (1 << 2); while (!(LPC_EMC->STATUS & (1 << 2))) {} #endif /* Shutdown perpheral clocks with wake up enabled */ Chip_Clock_StartPowerDown(); /* Get state of individual base clocks & store them for restoring. * Sets up the IRC as base clock source */ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { /* Get the Base clock settings */ Chip_Clock_GetBaseClockOpts(InitClkStates[i].clk, &InitClkStates[i].clkin, &InitClkStates[i].autoblock_enab, &InitClkStates[i].powerdn); /* Set IRC as clock input for all the base clocks */ Chip_Clock_SetBaseClock(InitClkStates[i].clk, CLKIN_IRC, InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); } /* Set IRC as clock source for SPIFI */ Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IRC, true, false); /* Set IRC as source clock for Core */ Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false); #ifdef BOARD_KEIL_MCB_18574357 /* Set Flash acceleration */ Chip_CREG_SetFlashAcceleration(CRYSTAL_MAIN_FREQ_IN); #endif /* Power down the main PLL */ Chip_Clock_DisableMainPLL(); Chip_Clock_DisablePLL(CGU_USB_PLL); Chip_Clock_DisableCrystal(); }
/** * @brief Main entry point * @return Nothing */ int main(void) { bool bool_status; uint32_t mainpll_freq, clkin_frq, dive_value, baseclk_frq, perclk_frq; CHIP_CGU_CLKIN_T clk_in, base_input; bool autoblocken; bool powerdn; int i; volatile int k = 1; SystemCoreClockUpdate(); Board_Init(); /* Print the Demo Information */ DEBUGOUT(menu); /* Main PLL should be locked, Check if Main PLL is locked */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("PLL functions \r\n"); DEBUGOUT("Main PLL : "); bool_status = Chip_Clock_MainPLLLocked(); if (bool_status == true) { DEBUGOUT("Locked\r\n"); } else { DEBUGOUT("Not Locked\r\n"); return 1; } /* Read Main PLL frequency in Hz */ mainpll_freq = Chip_Clock_GetMainPLLHz(); if (mainpll_freq == 0) { DEBUGOUT("Error in reading Main PLL frequency \r\n"); return 2; } DEBUGOUT("Main PLL Frequency in Hz : %d \r\n", mainpll_freq); DEBUGOUT("=========================================== \r\n"); DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Clock Divider functions \r\n"); /* * Divider E divider is used for SPIFI, source is set to * Main PLL in SysInit code. * Read Divider E source & verify it */ clk_in = Chip_Clock_GetDividerSource(CLK_IDIV_E); if (clk_in != CLKIN_MAINPLL) { DEBUGOUT("Divider E source wrong %d \r\n", clk_in); return 3; } DEBUGOUT("Divider E source set to Main PLL \r\n"); /* * Divider E divider is used for SPIFI, divider value should be * between 3 and 5 set in SysInit code. * Read Divider E divider value & verify it */ dive_value = Chip_Clock_GetDividerDivisor(CLK_IDIV_E); if ( (dive_value < 3) && (dive_value > 5)) { DEBUGOUT("Divider E divider wrong %d \r\n", dive_value); return 4; } DEBUGOUT("Divider E divider value: %d \r\n", dive_value); DEBUGOUT("=========================================== \r\n"); /* * Read the frequencies of the input clock sources, * print it on UART prompt */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Input clock frequencies \r\n"); DEBUGOUT("=========================================== \r\n"); for ( i = 0; i < (sizeof(clkin_info) / sizeof(CLKIN_NAME_T)); i++) { clkin_frq = Chip_Clock_GetClockInputHz(clkin_info[i].clk_in); DEBUGOUT(" %s Frequency : %d Hz \r\n", clkin_info[i].clkin_name, clkin_frq); } DEBUGOUT("=========================================== \r\n"); /* * Read the base clock settings & print on UART */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Base Clock Setting Information \r\n"); DEBUGOUT("=========================================== \r\n"); for ( i = 0; i < (sizeof(baseclk_info) / sizeof(BASECLK_INFO_T)); i++) { /* Read Base clock info, only if base clock is enabled */ bool_status = Chip_Clock_IsBaseClockEnabled(baseclk_info[i].clock); if ( bool_status == true) { Chip_Clock_GetBaseClockOpts(baseclk_info[i].clock, &base_input, &autoblocken, &powerdn); /* Read Frequency of the base clock */ baseclk_frq = Chip_Clock_GetBaseClocktHz(baseclk_info[i].clock); /* Print details on UART */ DEBUGOUT("%s Input Clk: %d Base Clk Frq : %d Hz Auto block: %d Power down: %d \r\n", baseclk_info[i].clock_name, base_input, baseclk_frq, autoblocken, powerdn); } } DEBUGOUT("=========================================== \r\n"); /* * Read the peripheral clock rate & print on UART */ DEBUGOUT("=========================================== \r\n"); DEBUGOUT("Peripheral Clock Rates \r\n"); DEBUGOUT("=========================================== \r\n"); for ( i = 0; i < (sizeof(ccu_clk_info) / sizeof(CCUCLK_INFO_T)); i++) { /* Read Frequency of the peripheral clock */ perclk_frq = Chip_Clock_GetRate(ccu_clk_info[i].per_clk); /* Print the per clock only if it is enabled */ if (perclk_frq) { /* Print details on UART */ DEBUGOUT("%s Per Frq : %d Hz \r\n", ccu_clk_info[i].clock_name, perclk_frq); } } DEBUGOUT("=========================================== \r\n"); while (k) ; return 0; }