/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* It is safe to switch the PLL Source to Crystal Oscillator */
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
/* Fout = FCCO / ((0+1) * 2) = 120MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(1);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
Chip_Clock_SetPCLKDiv(2);
}
void init_runtime_stats_timer( void )
{
Chip_TIMER_Init(LPC_TIMER3);
Chip_TIMER_Reset(LPC_TIMER3);
Chip_Clock_SetPCLKDiv(SYSCTL_PCLK_TIMER3, SYSCTL_CLKDIV_1);
Chip_TIMER_PrescaleSet(LPC_TIMER3, 3200);
Chip_TIMER_Enable(LPC_TIMER3);
}
/* common clock initialisation function
* This brings up enough clocks to allow the processor to run quickly while initialising memory.
* Other platform specific clock init can be done in init_platform() or init_host_mcu()
*/
WEAK void platform_init_system_clocks( void )
{
/* CPU clock source starts with IRC */
Chip_Clock_SetMainPllSource( SYSCTL_PLLCLKSRC_IRC );
Chip_Clock_SetCPUClockSource( SYSCTL_CCLKSRC_SYSCLK );
/* Enable main oscillator used for PLLs */
LPC_SYSCTL->SCS = SYSCTL_OSCEC;
while ( ( LPC_SYSCTL->SCS & SYSCTL_OSCSTAT ) == 0 )
{
}
/* PLL0 clock source is 12MHz oscillator, PLL1 can only be the
main oscillator */
Chip_Clock_SetMainPllSource( SYSCTL_PLLCLKSRC_MAINOSC );
/* Setup PLL0 for a 480MHz clock. It is divided by CPU Clock Divider to create CPU Clock.
Input clock rate (FIN) is main oscillator = 12MHz
FCCO is selected for PLL Output and it must be between 275 MHz to 550 MHz.
FCCO = (2 * M * FIN) / N = integer multiplier of CPU Clock (120MHz) = 480MHz
N = 1, M = 480 * 1/(2*12) = 20 */
Chip_Clock_SetupPLL( SYSCTL_MAIN_PLL, PLL_M_CONSTANT - 1, PLL_N_CONSTANT - 1 );/* Multiply by PLL_M_CONSTANT, Divide by PLL_N_CONSTANT */
/* Enable PLL0 */
Chip_Clock_EnablePLL( SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE );
/* Change the CPU Clock Divider setting for the operation with PLL0.
Divide value = (480/120) = 4 */
Chip_Clock_SetCPUClockDiv( 3 ); /* pre-minus 1 */
while ( !Chip_Clock_IsMainPLLLocked( ) )
{
}
/* Connect PLL0 */
Chip_Clock_EnablePLL( SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT );
/* Wait for PLL0 to be connected */
while ( !Chip_Clock_IsMainPLLConnected( ) )
{
}
/* Setup FLASH access to 5 clocks (120MHz clock) */
Chip_FMC_SetFLASHAccess( FLASHTIM_120MHZ_CPU );
/* Enable peripheral base clocks*/
Chip_Clock_SetPCLKDiv( SYSCTL_PCLK_SPI, SYSCTL_CLKDIV_1 );
Chip_RTC_Enable( LPC_RTC, ENABLE );
Chip_Clock_SetCLKOUTSource( SYSCTL_CLKOUTSRC_RTC, 1 );
Chip_Clock_EnableCLKOUT( );
}
