/* DMA routine for ADC example */
static void App_DMA_Test(void)
{
uint16_t dataADC;
/* Initialize GPDMA controller */
Chip_GPDMA_Init(LPC_GPDMA);
/* Setting GPDMA interrupt */
NVIC_DisableIRQ(DMA_IRQn);
NVIC_SetPriority(DMA_IRQn, ((0x01 << 3) | 0x01));
NVIC_EnableIRQ(DMA_IRQn);
/* Setting ADC interrupt, ADC Interrupt must be disable in DMA mode */
NVIC_DisableIRQ(_LPC_ADC_IRQ);
Chip_ADC_Int_SetChannelCmd(_LPC_ADC_ID, _ADC_CHANNLE, ENABLE);
/* Get the free channel for DMA transfer */
dmaChannelNum = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, _GPDMA_CONN_ADC);
/* Enable burst mode if any, the AD converter does repeated conversions
at the rate selected by the CLKS field in burst mode automatically */
if (Burst_Mode_Flag) {
Chip_ADC_SetBurstCmd(_LPC_ADC_ID, ENABLE);
}
/* Get adc value until get 'x' character */
while (DEBUGIN() != 'x') {
/* Start A/D conversion if not using burst mode */
if (!Burst_Mode_Flag) {
Chip_ADC_SetStartMode(_LPC_ADC_ID, ADC_START_NOW, ADC_TRIGGERMODE_RISING);
}
channelTC = 0;
Chip_GPDMA_Transfer(LPC_GPDMA, dmaChannelNum,
_GPDMA_CONN_ADC,
(uint32_t) &DMAbuffer,
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA,
1);
/* Waiting for reading ADC value completed */
while (channelTC == 0) {}
/* Get the ADC value fron Data register*/
dataADC = ADC_DR_RESULT(DMAbuffer);
App_print_ADC_value(dataADC);
}
/* Disable interrupts, release DMA channel */
Chip_GPDMA_Stop(LPC_GPDMA, dmaChannelNum);
NVIC_DisableIRQ(DMA_IRQn);
/* Disable burst mode if any */
if (Burst_Mode_Flag) {
Chip_ADC_SetBurstCmd(_LPC_ADC_ID, DISABLE);
}
}
void DMA_IRQHandler(void)
{
NVIC_DisableIRQ(DMA_IRQn);
if (Chip_GPDMA_Interrupt(LPC_GPDMA, dacInfo.dmaChannelDAC) == SUCCESS)
{
Chip_GPDMA_Stop(LPC_GPDMA, dacInfo.dmaChannelDAC);
if(dacInfo.flagCyclic)
{
Chip_GPDMA_Transfer(LPC_GPDMA, dacInfo.dmaChannelDAC,
(uint32_t) &dacInfo.dmaBuffer, GPDMA_CONN_DAC,
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA, dacInfo.samples);
NVIC_EnableIRQ(DMA_IRQn);
}
}
else
{
NVIC_EnableIRQ(DMA_IRQn);
}
}
int32_t Board_DAC_writeDMA(uint16_t* buffer, uint32_t size, bool flagCyclic)
{
int32_t ret = -1;
if (size != 0)
{
NVIC_DisableIRQ(DMA_IRQn);
dacInfo.flagCyclic = flagCyclic;
for (dacInfo.samples=0; dacInfo.samples<size; dacInfo.samples++)
{
dacInfo.dmaBuffer[dacInfo.samples] = (uint32_t) (DAC_VALUE(buffer[dacInfo.samples]));
if(dacInfo.flagEnableBias)
dacInfo.dmaBuffer[dacInfo.samples]|= DAC_BIAS_EN;
if(dacInfo.samples>= DMA_FIFO_SIZE)
break;
}
if(dacInfo.dmaChannelDAC==0xFF)
{
/* Get the free channel for DMA transfer */
dacInfo.dmaChannelDAC = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, GPDMA_CONN_DAC);
}
else
{
Chip_GPDMA_Stop(LPC_GPDMA, dacInfo.dmaChannelDAC);
}
/* Start DMA transfer */
Chip_GPDMA_Transfer(LPC_GPDMA, dacInfo.dmaChannelDAC,
(uint32_t) &dacInfo.dmaBuffer, GPDMA_CONN_DAC,
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA, dacInfo.samples);
ret = dacInfo.samples*2;
NVIC_EnableIRQ(DMA_IRQn);
}
return ret;
}
/* Select the Transfer mode : Polling, Interrupt or DMA */
static void appSSPTest(void)
{
int key;
DEBUGOUT(sspTransferModeSel);
dmaChSSPTx = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, LPC_GPDMA_SSP_TX);
dmaChSSPRx = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, LPC_GPDMA_SSP_RX);
xf_setup.length = BUFFER_SIZE;
xf_setup.tx_data = Tx_Buf;
xf_setup.rx_data = Rx_Buf;
while (1) {
key = 0xFF;
do {
key = DEBUGIN();
} while ((key & 0xFF) == 0xFF);
Buffer_Init();
switch (key) {
case SSP_POLLING_SEL: /* SSP Polling Read Write Mode */
DEBUGOUT(sspWaitingMenu);
xf_setup.rx_cnt = xf_setup.tx_cnt = 0;
Chip_SSP_RWFrames_Blocking(LPC_SSP, &xf_setup);
if (Buffer_Verify() == 0) {
DEBUGOUT(sspPassedMenu);
}
else {
DEBUGOUT(sspFailedMenu);
}
break;
case SSP_INTERRUPT_SEL:
DEBUGOUT(sspIntWaitingMenu);
isXferCompleted = 0;
xf_setup.rx_cnt = xf_setup.tx_cnt = 0;
Chip_SSP_Int_FlushData(LPC_SSP);/* flush dummy data from SSP FiFO */
if (SSP_DATA_BYTES(ssp_format.bits) == 1) {
Chip_SSP_Int_RWFrames8Bits(LPC_SSP, &xf_setup);
}
else {
Chip_SSP_Int_RWFrames16Bits(LPC_SSP, &xf_setup);
}
Chip_SSP_Int_Enable(LPC_SSP); /* enable interrupt */
while (!isXferCompleted) {}
if (Buffer_Verify() == 0) {
DEBUGOUT(sspPassedMenu);
}
else {
DEBUGOUT(sspFailedMenu);
}
break;
case SSP_DMA_SEL: /* SSP DMA Read and Write: fixed on 8bits */
DEBUGOUT(sspDMAWaitingMenu);
isDmaTxfCompleted = isDmaRxfCompleted = 0;
Chip_SSP_DMA_Enable(LPC_SSP);
/* data Tx_Buf --> SSP */
Chip_GPDMA_Transfer(LPC_GPDMA, dmaChSSPTx,
(uint32_t) &Tx_Buf[0],
LPC_GPDMA_SSP_TX,
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA,
BUFFER_SIZE);
/* data SSP --> Rx_Buf */
Chip_GPDMA_Transfer(LPC_GPDMA, dmaChSSPRx,
LPC_GPDMA_SSP_RX,
(uint32_t) &Rx_Buf[0],
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA,
BUFFER_SIZE);
while (!isDmaTxfCompleted || !isDmaRxfCompleted) {}
if (Buffer_Verify() == 0) {
DEBUGOUT(sspPassedMenu);
}
else {
DEBUGOUT(sspFailedMenu);
}
Chip_SSP_DMA_Disable(LPC_SSP);
break;
case 'q':
case 'Q':
Chip_GPDMA_Stop(LPC_GPDMA, dmaChSSPTx);
Chip_GPDMA_Stop(LPC_GPDMA, dmaChSSPRx);
return;
default:
break;
}
DEBUGOUT(sspTransferModeSel);
}
}
/* DeInitialize DMA for UART, free transfer channels and disable DMA interrupt */
static void App_DMA_DeInit(void)
{
Chip_GPDMA_Stop(LPC_GPDMA, dmaChannelNumTx);
Chip_GPDMA_Stop(LPC_GPDMA, dmaChannelNumRx);
NVIC_DisableIRQ(DMA_IRQn);
}
