func Initialize()
{
_inherited();
SetSkyParallax(1, 20,20, 0,0, SkyPar_Keep(),SkyPar_Keep());
CreateGate(SGR2,STGT, 2555, 280, -1,"Jaffa");
CreateObject(DHD_,2503,185,-1);
CreateGate(SGR2,STGT, 2553, 1378, -1,"Wraith");
CreateObject(DHD_,2478,1375,-1);
UpdateScoreboard();
helper = 1;
ScriptGo(0);
return(1);
}
void DrawCmd::DrawGate( int flag )
{
AcDbObjectId objId = ArxUtilHelper::SelectObject( _T( "请选择一个巷道、硐室:" ) );
if( objId.isNull() ) return;
if( !ArxUtilHelper::IsEqualType( _T( "Tunnel" ), objId ) &&
!ArxUtilHelper::IsEqualType( _T( "StorageGE" ), objId ) ) return;
AcGePoint3d pt;
if( !PromptInsertPt( objId, pt ) ) return;
double angle;
if( !GetClosePtAndAngle( objId, pt, angle ) ) return;
CreateGate( flag, objId, pt, angle );
}
func Initialize()
{
CreateGate(SGR3, SGDG, 515, 298, -1, "Alienworld");
CreateGate(SGR2, SGAG, 2007, 1570, -1, "Pandora");
CreateGate(SGR3, SGDG, 2507, 3131, -1, "Dune");
CreateGate(SGR2, STGT, 347, 4151, -1, "Deathstar");
CreateGate(SGR2, SGAG, 2010, 5321, -1, "Thalus");
CreateGate(SGR3, SGDG, 3504, 5983, -1, "Lavahöhlen");
CreateGate(SGR1, STGT, 1596, 6987, -1, "Mond");
CreateObject(DHD_, 1514, 7000, -1);
CreateObject(DHD_, 272, 4148, -1);
CreateObject(DHDP, 1926, 5317, -1);
CreateObject(DHDP, 1929, 1568, -1);
CreateObject(DHDD, 428, 292, -1);
CreateObject(DHDD, 3418, 5978, -1);
CreateObject(DHDD, 2419, 3128, -1);
return(1);
}
bool netlistreader_verilog::read(netlist *netl, sim_data *simul_data) {
gate* p_gate = NULL;
//size_t i = 0;
netl->neededSteps = 0;
bool gateInputs = false;
bool readStates = false;
bool readNames = false;
bool readModule = false;
Event ev;
ev.time=0;
int currentTime = 0;
int time = 0;
if(!tokenize())
return false;
for (size_t i = 0; i < tokens.size(); i++) {
if (tokens[i].pos == 1) {
gateInputs = false;
readStates = false;
readNames = false;
}
// ќбработчик $dumpfile, пока без $dumpvars
if(tokens[i].item == "$dumpfile") {
std::string vcdname;
i=i+2;
while(tokens[i].item != ")") {
if(tokens[i].item != "\"") {
vcdname = vcdname + tokens[i].item;
}
++i;
}
simul_data->setVCDname(vcdname);
}
//New module for Verilog (basic)
if (readModule) {
if ((tokens[i].item == "input") || ((tokens[i].item == "output") && (tokens[i].pos == 1))) {
}
if ((tokens[i].item == "nor") || (tokens[i].item == "nand") || (tokens[i].item == "or") || (tokens[i].item == "and") || (tokens[i].item == "not") || (tokens[i].item == "xor") || (tokens[i].item == "xnor") || (tokens[i].item == "buf")) {
p_gate = CreateGate(tokens[i + 1].item, tokens[i].item);
if (!p_gate)
continue;
p_gate->repeat = 0;
netl->addGate(p_gate);
p_gate->outs.push_back(netl->addNet(tokens[i + 3].item, NULL));
gateInputs = true;
i += 4;
}
if (gateInputs) {
while (tokens[i].item != ")") {
if (tokens[i].item != ",") {
p_gate->ins.push_back(netl->addNet(tokens[i].item, p_gate));
}
i++;
}
gateInputs = false;
}
}
if ((tokens[i].item == "module") && (tokens[i].pos == 1)) {
i += 3;
/*
while (tokens[i].item != ")") {
if (tokens[i].item != ",") {
simul_data->dumpNames.push_back(tokens[i].item);
}
i++;
}
*/
readModule = true;
}
if ((tokens[i].item == "endmodule")) {
readModule = false;
}
if ((tokens[i].item == "#")/* && (tokens[i].pos == 1)*/) {
currentTime = atoi(tokens[i+1].item.c_str());
i++;
time += currentTime;
i++;
// ev = *(simul_data->addEvent(time, netl->returnNet(tokens[i].item), LogicLevel(atoi(tokens[i + 2].item.c_str()))));
while((tokens[i].item != "#") || (tokens[i].item != "$finish")) {
if((tokens[i].item == "#") || (tokens[i].item == "$finish")) {
i--;
break;
}
ev = *(simul_data->addEvent(time, netl->addNet(tokens[i].item, NULL), LogicLevel(atoi(tokens[i + 2].item.c_str()))));
i += 4;
}
}
}
for(size_t i = 0; i < netl->gates.size(); ++i)
if(!netl->gates[i]->postprocess())
return false;
return true;
}
