/*******************************************************************************
* Function Name: USBUART_Suspend
********************************************************************************
*
* Summary:
* This function disables the USBFS block and prepares for power down mode.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* USBUART_backup.enable: modified.
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBUART_Suspend(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if((CY_GET_REG8(USBUART_CR0_PTR) & USBUART_CR0_ENABLE) != 0u)
{ /* USB block is enabled */
USBUART_backup.enableState = 1u;
#if(USBUART_EP_MM != USBUART__EP_MANUAL)
USBUART_Stop_DMA(USBUART_MAX_EP); /* Stop all DMAs */
#endif /* USBUART_EP_MM != USBUART__EP_MANUAL */
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
USBUART_USBIO_CR0_REG &= (uint8)~USBUART_USBIO_CR0_TEN;
CyDelayUs(0u); /*~50ns delay */
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */
USBUART_PM_USB_CR0_REG &=
(uint8)~(USBUART_PM_USB_CR0_PD_N | USBUART_PM_USB_CR0_PD_PULLUP_N);
/* Disable the SIE */
USBUART_CR0_REG &= (uint8)~USBUART_CR0_ENABLE;
CyDelayUs(0u); /* ~50ns delay */
/* Store mode and Disable VRegulator*/
USBUART_backup.mode = USBUART_CR1_REG & USBUART_CR1_REG_ENABLE;
USBUART_CR1_REG &= (uint8)~USBUART_CR1_REG_ENABLE;
CyDelayUs(1u); /* 0.5 us min delay */
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG &= (uint8)~USBUART_PM_USB_CR0_REF_EN;
/* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/
USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;
/* Disable USB in ACT PM */
USBUART_PM_ACT_CFG_REG &= (uint8)~USBUART_PM_ACT_EN_FSUSB;
/* Disable USB block for Standby Power Mode */
USBUART_PM_STBY_CFG_REG &= (uint8)~USBUART_PM_STBY_EN_FSUSB;
CyDelayUs(1u); /* min 0.5us delay required */
}
else
{
USBUART_backup.enableState = 0u;
}
CyExitCriticalSection(enableInterrupts);
/* Set the DP Interrupt for wake-up from sleep mode. */
#if(USBUART_DP_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBUART_DP_INTC_VECT_NUM, &USBUART_DP_ISR);
CyIntSetPriority(USBUART_DP_INTC_VECT_NUM, USBUART_DP_INTC_PRIOR);
CyIntClearPending(USBUART_DP_INTC_VECT_NUM);
CyIntEnable(USBUART_DP_INTC_VECT_NUM);
#endif /* (USBUART_DP_ISR_REMOVE == 0u) */
}
/*****************************************************************************
* Function Name: WatchdogTimer_Sync()
******************************************************************************
* Summary:
* Synchronizes the watchdog timestamp to the current system time.
*
* Parameters:
* None
*
* Return:
* None
*
* Theory:
* Updates the watchdog timestamp to the current value.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
void WatchdogTimer_Sync(void)
{
uint32 wdtIntState;
uint16 wdtCounter;
uint16 wdtPreviousMatch;
uint16 wdtCurrentMatch;
uint16 ticksElapsed;
/* Capture the WDT interrupt enable and disable the WDT interrupt. */
wdtIntState = CyIntGetState(WDT_INTERRUPT_NUM);
CyIntDisable(WDT_INTERRUPT_NUM);
wdtCounter = CY_GET_REG32(CYREG_WDT_CTRLOW);
wdtCurrentMatch = CY_GET_REG32(CYREG_WDT_MATCH);
/* Find time elapsed since last WDT interrupt */
wdtPreviousMatch = wdtCurrentMatch - nextTicks;
ticksElapsed = wdtCounter - wdtPreviousMatch;
watchdogTimestamp += ticksElapsed / WATCHDOG_TICKS_PER_MS;
/* Add slow timer period to match register for next interrupt */
WatchdogTimer_Unlock();
UPDATE_WDT_MATCH((uint16)(wdtCounter + nextTicks -
(ticksElapsed % WATCHDOG_TICKS_PER_MS)));
/* Clear pending WDT interrupt */
CY_SET_REG32(CYREG_WDT_CONTROL, CY_GET_REG32(CYREG_WDT_CONTROL) | WDT_CONTROL_WDT_INT0);
CyIntClearPending(WDT_INTERRUPT_NUM);
WatchdogTimer_Lock();
/* Restore WDT interrupt enable */
if(wdtIntState)
{
CyIntEnable(WDT_INTERRUPT_NUM);
}
}
/*******************************************************************************
* Function Name: TPS_ADC_SAR_Enable
********************************************************************************
*
* Summary:
* Enables the reference, clock and power for SAR ADC.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void TPS_ADC_SAR_Enable(void)
{
uint8 tmpReg;
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
/* Enable the SAR ADC block in Active Power Mode */
TPS_ADC_SAR_PWRMGR_SAR_REG |= TPS_ADC_SAR_ACT_PWR_SAR_EN;
/* Enable the SAR ADC in Standby Power Mode*/
TPS_ADC_SAR_STBY_PWRMGR_SAR_REG |= TPS_ADC_SAR_STBY_PWR_SAR_EN;
/* This is only valid if there is an internal clock */
#if(TPS_ADC_SAR_DEFAULT_INTERNAL_CLK)
TPS_ADC_SAR_PWRMGR_CLK_REG |= TPS_ADC_SAR_ACT_PWR_CLK_EN;
TPS_ADC_SAR_STBY_PWRMGR_CLK_REG |= TPS_ADC_SAR_STBY_PWR_CLK_EN;
#endif /* End TPS_ADC_SAR_DEFAULT_INTERNAL_CLK */
/* Enable VCM buffer and Enable Int Ref Amp */
tmpReg = TPS_ADC_SAR_SAR_CSR3_REG;
tmpReg |= TPS_ADC_SAR_SAR_EN_BUF_VCM_EN;
/* PD_BUF_VREF is OFF in External reference or Vdda reference mode */
#if((TPS_ADC_SAR_DEFAULT_REFERENCE == TPS_ADC_SAR__EXT_REF) || \
(TPS_ADC_SAR_DEFAULT_RANGE == TPS_ADC_SAR__VNEG_VDDA_DIFF))
tmpReg &= (uint8)~TPS_ADC_SAR_SAR_EN_BUF_VREF_EN;
#else /* In INTREF or INTREF Bypassed this buffer is ON */
tmpReg |= TPS_ADC_SAR_SAR_EN_BUF_VREF_EN;
#endif /* TPS_ADC_SAR_DEFAULT_REFERENCE == TPS_ADC_SAR__EXT_REF */
TPS_ADC_SAR_SAR_CSR3_REG = tmpReg;
/* Set reference for ADC */
#if(TPS_ADC_SAR_DEFAULT_RANGE == TPS_ADC_SAR__VNEG_VDDA_DIFF)
#if(TPS_ADC_SAR_DEFAULT_REFERENCE == TPS_ADC_SAR__EXT_REF)
TPS_ADC_SAR_SAR_CSR6_REG = TPS_ADC_SAR_INT_BYPASS_EXT_VREF; /* S2 */
#else /* Internal Vdda reference or obsolete bypass mode */
TPS_ADC_SAR_SAR_CSR6_REG = TPS_ADC_SAR_VDDA_VREF; /* S7 */
#endif /* TPS_ADC_SAR_DEFAULT_REFERENCE == TPS_ADC_SAR__EXT_REF */
#else /* Reference goes through internal buffer */
#if(TPS_ADC_SAR_DEFAULT_REFERENCE == TPS_ADC_SAR__INT_REF_NOT_BYPASSED)
TPS_ADC_SAR_SAR_CSR6_REG = TPS_ADC_SAR_INT_VREF; /* S3 + S4 */
#else /* INTREF Bypassed of External */
TPS_ADC_SAR_SAR_CSR6_REG = TPS_ADC_SAR_INT_BYPASS_EXT_VREF; /* S2 */
#endif /* TPS_ADC_SAR_DEFAULT_REFERENCE == TPS_ADC_SAR__INT_REF_NOT_BYPASSED */
#endif /* VNEG_VDDA_DIFF */
/* Low non-overlap delay for sampling clock signals (for 1MSPS) */
#if(TPS_ADC_SAR_HIGH_POWER_PULSE == 0u) /* MinPulseWidth <= 50 ns */
TPS_ADC_SAR_SAR_CSR5_REG &= (uint8)~TPS_ADC_SAR_SAR_DLY_INC;
#else /* Set High non-overlap delay for sampling clock signals (for <500KSPS)*/
TPS_ADC_SAR_SAR_CSR5_REG |= TPS_ADC_SAR_SAR_DLY_INC;
#endif /* TPS_ADC_SAR_HIGH_POWER_PULSE == 0u */
/* Increase comparator latch enable delay by 20%,
* Increase comparator bias current by 30% without impacting delaysDelay
* Default for 1MSPS)
*/
#if(TPS_ADC_SAR_HIGH_POWER_PULSE == 0u) /* MinPulseWidth <= 50 ns */
TPS_ADC_SAR_SAR_CSR5_REG |= TPS_ADC_SAR_SAR_SEL_CSEL_DFT_CHAR;
#else /* for <500ksps */
TPS_ADC_SAR_SAR_CSR5_REG &= (uint8)~TPS_ADC_SAR_SAR_SEL_CSEL_DFT_CHAR;
#endif /* TPS_ADC_SAR_HIGH_POWER_PULSE == 0u */
/* Set default power and other configurations for control register 0 in multiple lines */
TPS_ADC_SAR_SAR_CSR0_REG = (uint8)((uint8)TPS_ADC_SAR_DEFAULT_POWER << TPS_ADC_SAR_SAR_POWER_SHIFT)
/* SAR_HIZ_CLEAR: Should not be used for LP */
#if ((CY_PSOC5LP) || (TPS_ADC_SAR_DEFAULT_REFERENCE != TPS_ADC_SAR__EXT_REF))
| TPS_ADC_SAR_SAR_HIZ_CLEAR
#endif /* SAR_HIZ_CLEAR */
/*Set Convertion mode */
#if(TPS_ADC_SAR_DEFAULT_CONV_MODE != TPS_ADC_SAR__FREE_RUNNING) /* If triggered mode */
| TPS_ADC_SAR_SAR_MX_SOF_UDB /* source: UDB */
| TPS_ADC_SAR_SAR_SOF_MODE_EDGE /* Set edge-sensitive sof source */
#endif /* TPS_ADC_SAR_DEFAULT_CONV_MODE */
; /* end of multiple line initialization */
TPS_ADC_SAR_SAR_TR0_REG = TPS_ADC_SAR_SAR_CAP_TRIM_2;
/* Enable clock for SAR ADC*/
TPS_ADC_SAR_SAR_CLK_REG |= TPS_ADC_SAR_SAR_MX_CLK_EN;
CyDelayUs(10u); /* The block is ready to use 10 us after the enable signal is set high. */
#if(TPS_ADC_SAR_IRQ_REMOVE == 0u)
/* Clear a pending interrupt */
CyIntClearPending(TPS_ADC_SAR_INTC_NUMBER);
#endif /* End TPS_ADC_SAR_IRQ_REMOVE */
CyExitCriticalSection(enableInterrupts);
}
/*******************************************************************************
* Function Name: ADC_SAR_1_Enable
********************************************************************************
*
* Summary:
* Enables the reference, clock and power for SAR ADC.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void ADC_SAR_1_Enable(void)
{
uint8 tmpReg;
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
/* Enable the SAR ADC block in Active Power Mode */
ADC_SAR_1_PWRMGR_SAR_REG |= ADC_SAR_1_ACT_PWR_SAR_EN;
/* Enable the SAR ADC in Standby Power Mode*/
ADC_SAR_1_STBY_PWRMGR_SAR_REG |= ADC_SAR_1_STBY_PWR_SAR_EN;
/* This is only valid if there is an internal clock */
#if(ADC_SAR_1_DEFAULT_INTERNAL_CLK)
ADC_SAR_1_PWRMGR_CLK_REG |= ADC_SAR_1_ACT_PWR_CLK_EN;
ADC_SAR_1_STBY_PWRMGR_CLK_REG |= ADC_SAR_1_STBY_PWR_CLK_EN;
#endif /* End ADC_SAR_1_DEFAULT_INTERNAL_CLK */
/* Enable VCM buffer and Enable Int Ref Amp */
tmpReg = ADC_SAR_1_SAR_CSR3_REG;
#if(CY_PSOC5A) /* Make sure that full power is applied for VREF buffer */
tmpReg &= (uint8)~ADC_SAR_1_SAR_PWR_CTRL_VREF_DIV_BY4;
#endif /* CY_PSOC5A */
tmpReg |= ADC_SAR_1_SAR_EN_BUF_VCM_EN;
/* PD_BUF_VREF is OFF in External reference or Vdda reference mode */
#if((ADC_SAR_1_DEFAULT_REFERENCE == ADC_SAR_1__EXT_REF) || \
(ADC_SAR_1_DEFAULT_RANGE == ADC_SAR_1__VNEG_VDDA_DIFF))
tmpReg &= (uint8)~ADC_SAR_1_SAR_EN_BUF_VREF_EN;
#else /* In INTREF or INTREF Bypassed this buffer is ON */
tmpReg |= ADC_SAR_1_SAR_EN_BUF_VREF_EN;
#endif /* ADC_SAR_1_DEFAULT_REFERENCE == ADC_SAR_1__EXT_REF */
ADC_SAR_1_SAR_CSR3_REG = tmpReg;
/* Set reference for ADC */
#if(ADC_SAR_1_DEFAULT_RANGE == ADC_SAR_1__VNEG_VDDA_DIFF)
#if(ADC_SAR_1_DEFAULT_REFERENCE == ADC_SAR_1__EXT_REF)
ADC_SAR_1_SAR_CSR6_REG = ADC_SAR_1_INT_BYPASS_EXT_VREF; /* S2 */
#else /* Internal Vdda reference or obsolete bypass mode */
ADC_SAR_1_SAR_CSR6_REG = ADC_SAR_1_VDDA_VREF; /* S7 */
#endif /* ADC_SAR_1_DEFAULT_REFERENCE == ADC_SAR_1__EXT_REF */
#else /* Reference goes through internal buffer */
#if(ADC_SAR_1_DEFAULT_REFERENCE == ADC_SAR_1__INT_REF_NOT_BYPASSED)
ADC_SAR_1_SAR_CSR6_REG = ADC_SAR_1_INT_VREF; /* S3 + S4 */
#else /* INTREF Bypassed of External */
ADC_SAR_1_SAR_CSR6_REG = ADC_SAR_1_INT_BYPASS_EXT_VREF; /* S2 */
#endif /* ADC_SAR_1_DEFAULT_REFERENCE == ADC_SAR_1__INT_REF_NOT_BYPASSED */
#endif /* VNEG_VDDA_DIFF */
/* Low non-overlap delay for sampling clock signals (for 1MSPS) */
#if(ADC_SAR_1_HIGH_POWER_PULSE == 0u) /* MinPulseWidth <= 50 ns */
ADC_SAR_1_SAR_CSR5_REG &= (uint8)~ADC_SAR_1_SAR_DLY_INC;
#else /* Set High non-overlap delay for sampling clock signals (for <500KSPS)*/
ADC_SAR_1_SAR_CSR5_REG |= ADC_SAR_1_SAR_DLY_INC;
#endif /* ADC_SAR_1_CLOCK_FREQUENCY > (ADC_SAR_1_MAX_FREQUENCY / 2) */
/* Delay control for comparator latch enable, low delay, (Default for 1MSPS) */
#if(ADC_SAR_1_HIGH_POWER_PULSE == 0u) /* MinPulseWidth <= 50 ns */
ADC_SAR_1_SAR_CSR5_REG |= ADC_SAR_1_SAR_DCEN;
#else /* Delay control for comparator latch enable, high delay (for <500ksps)*/
ADC_SAR_1_SAR_CSR5_REG &= (uint8)~ADC_SAR_1_SAR_DCEN;
#endif /* ADC_SAR_1_CLOCK_FREQUENCY > (ADC_SAR_1_MAX_FREQUENCY / 2) */
/* Set default power and other configurations for control register 0 in multiple lines */
ADC_SAR_1_SAR_CSR0_REG = (uint8)((uint8)ADC_SAR_1_DEFAULT_POWER << ADC_SAR_1_SAR_POWER_SHIFT)
/* SAR_HIZ_CLEAR: Should not be used for LP */
#if ((CY_PSOC5LP) || (ADC_SAR_1_DEFAULT_REFERENCE != ADC_SAR_1__EXT_REF))
| ADC_SAR_1_SAR_HIZ_CLEAR
#endif /* SAR_HIZ_CLEAR */
/*Set Convertion mode */
#if(ADC_SAR_1_DEFAULT_CONV_MODE != ADC_SAR_1__FREE_RUNNING) /* If triggered mode */
| ADC_SAR_1_SAR_MX_SOF_UDB /* source: UDB */
| ADC_SAR_1_SAR_SOF_MODE_EDGE /* Set edge-sensitive sof source */
#endif /* ADC_SAR_1_DEFAULT_CONV_MODE */
; /* end of multiple line initialization */
/* Enable clock for SAR ADC*/
ADC_SAR_1_SAR_CLK_REG |= ADC_SAR_1_SAR_MX_CLK_EN;
#if(CY_PSOC5A)
/* Software Reset */
ADC_SAR_1_SAR_CSR0_REG |= ADC_SAR_1_SAR_RESET_SOFT_ACTIVE;
CyDelayUs(2u); /* 2us delay is required for the lowest 1Mhz clock connected to SAR */
ADC_SAR_1_SAR_CSR0_REG &= (uint8)~ADC_SAR_1_SAR_RESET_SOFT_ACTIVE;
#else
CyDelayUs(10u); /* The block is ready to use 10 us after the enable signal is set high. */
#endif /* End CY_PSOC5A */
#if(ADC_SAR_1_IRQ_REMOVE == 0u)
/* Clear a pending interrupt */
CyIntClearPending(ADC_SAR_1_INTC_NUMBER);
#endif /* End ADC_SAR_1_IRQ_REMOVE */
CyExitCriticalSection(enableInterrupts);
}
/*******************************************************************************
* Function Name: I2C_MasterWriteBuf
********************************************************************************
*
* Summary:
* Automatically writes an entire buffer of data to a slave device. Once the
* data transfer is initiated by this function, further data transfer is handled
* by the included ISR in byte by byte mode.
*
* Parameters:
* slaveAddr: 7-bit slave address.
* xferData: Pointer to buffer of data to be sent.
* cnt: Size of buffer to send.
* mode: Transfer mode defines: start or restart condition generation at
* begin of the transfer and complete the transfer or halt before
* generating a stop.
*
* Return:
* Status error - zero means no errors.
*
* Side Effects:
* The included ISR will start transfer after start or restart condition will
* be generated.
*
* Global variables:
* I2C_mstrStatus - used to store current status of I2C Master.
* I2C_state - used to store current state of software FSM.
* I2C_mstrControl - used to control master end of transaction with
* or without the Stop generation.
* I2C_mstrWrBufPtr - used to store pointer to master write buffer.
* I2C_mstrWrBufIndex - used to current index within master write
* buffer.
* I2C_mstrWrBufSize - used to store master write buffer size.
*
* Reentrant:
* No
*
*******************************************************************************/
uint8 I2C_MasterWriteBuf(uint8 slaveAddress, uint8 * wrData, uint8 cnt, uint8 mode)
{
uint8 errStatus;
errStatus = I2C_MSTR_NOT_READY;
if(NULL != wrData)
{
/* Check I2C state before transfer: valid are IDLE or HALT */
if(I2C_SM_IDLE == I2C_state)
{
/* Check if free: Master is ready to transaction */
if(I2C_CHECK_BUS_FREE(I2C_MCSR_REG))
{
errStatus = I2C_MSTR_NO_ERROR;
}
else
{
errStatus = I2C_MSTR_BUS_BUSY;
}
}
else if(I2C_SM_MSTR_HALT == I2C_state)
{
errStatus = I2C_MSTR_NO_ERROR;
CyIntClearPending(I2C_ISR_NUMBER);
I2C_mstrStatus &= ((uint8) ~I2C_MSTAT_XFER_HALT);
}
else
{
/* errStatus = I2C_MSTR_NOT_READY was send before */
}
if(I2C_MSTR_NO_ERROR == errStatus)
{
I2C_state = I2C_SM_MSTR_WR_ADDR;
I2C_DATA_REG = ((uint8) (slaveAddress << I2C_SLAVE_ADDR_SHIFT));
I2C_mstrWrBufIndex = 0u;
I2C_mstrWrBufSize = cnt;
I2C_mstrWrBufPtr = (volatile uint8 *) wrData;
I2C_mstrControl = mode; /* Save transaction mode */
/* Generate a Start or ReStart depends on mode */
if(I2C_CHECK_RESTART(mode))
{
I2C_GENERATE_RESTART;
}
else
{
I2C_GENERATE_START;
}
I2C_mstrStatus &= ((uint8) ~I2C_MSTAT_WR_CMPLT);
I2C_EnableInt(); /* Enable intr to complete transfer */
}
}
return(errStatus);
}
/*******************************************************************************
* Function Name: OSC1_ADC_SAR_Enable
********************************************************************************
*
* Summary:
* Enables DMA channels, address selection counter and FSM of Base component
*
* Parameters:
* None.
*
* Return:
* None.
*
* Side Effects:
* None.
*
* Reentrant:
* No.
*
*******************************************************************************/
void OSC1_ADC_SAR_Enable(void)
{
uint8 enableInterrupts;
static int16 OSC1_ADC_SAR_tempArray[OSC1_ADC_SAR_NUMBER_OF_CHANNELS];
(void)CyDmaClearPendingDrq(OSC1_ADC_SAR_tempChan);
(void)CyDmaClearPendingDrq(OSC1_ADC_SAR_finalChan);
/* Provides initialization procedure for the TempBuf DMA
* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the destination address, but not the source address
*/
if (OSC1_ADC_SAR_tempTD == DMA_INVALID_TD)
{
OSC1_ADC_SAR_tempTD = CyDmaTdAllocate();
}
(void) CyDmaTdSetConfiguration(OSC1_ADC_SAR_tempTD, OSC1_ADC_SAR_TEMP_TRANSFER_COUNT,
OSC1_ADC_SAR_tempTD, ((uint8)OSC1_ADC_SAR_TempBuf__TD_TERMOUT_EN | (uint8)TD_INC_DST_ADR));
/* From the SAR to the TempArray */
(void) CyDmaTdSetAddress(OSC1_ADC_SAR_tempTD, (uint16)(LO16((uint32)OSC1_ADC_SAR_SAR_DATA_ADDR_0)),
(uint16)(LO16((uint32)OSC1_ADC_SAR_tempArray)));
/* Associate the TD with the channel */
(void) CyDmaChSetInitialTd(OSC1_ADC_SAR_tempChan, OSC1_ADC_SAR_tempTD);
/* Provides initialization procedure for the FinalBuf DMA
* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the source and destination address
*/
if (OSC1_ADC_SAR_finalTD == DMA_INVALID_TD)
{
OSC1_ADC_SAR_finalTD = CyDmaTdAllocate();
}
(void) CyDmaTdSetConfiguration(OSC1_ADC_SAR_finalTD, (OSC1_ADC_SAR_FINAL_BYTES_PER_BURST),
OSC1_ADC_SAR_finalTD, ((uint8)(OSC1_ADC_SAR_FinalBuf__TD_TERMOUT_EN) | (uint8)TD_INC_SRC_ADR |
(uint8)TD_INC_DST_ADR));
/* From the the TempArray to Final Array */
(void) CyDmaTdSetAddress(OSC1_ADC_SAR_finalTD, (uint16)(LO16((uint32)OSC1_ADC_SAR_tempArray)),
(uint16)(LO16((uint32)OSC1_ADC_SAR_finalArray)));
/* Associate the TD with the channel */
(void) CyDmaChSetInitialTd(OSC1_ADC_SAR_finalChan, OSC1_ADC_SAR_finalTD);
(void) CyDmaChEnable(OSC1_ADC_SAR_tempChan, 1u);
(void) CyDmaChEnable(OSC1_ADC_SAR_finalChan, 1u);
/* Enable Counter and give Enable pulse to set an address of the last channel */
enableInterrupts = CyEnterCriticalSection();
OSC1_ADC_SAR_CYCLE_COUNTER_AUX_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_CYCLE_COUNTER_ENABLE));
CyExitCriticalSection(enableInterrupts);
/* Enable FSM of the Base Component */
OSC1_ADC_SAR_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_BASE_COMPONENT_ENABLE));
OSC1_ADC_SAR_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_LOAD_COUNTER_PERIOD));
#if(OSC1_ADC_SAR_IRQ_REMOVE == 0u)
/* Clear a pending interrupt */
CyIntClearPending(OSC1_ADC_SAR_INTC_NUMBER);
#endif /* End OSC1_ADC_SAR_IRQ_REMOVE */
}
/*******************************************************************************
* Function Name: USBUART_Suspend
****************************************************************************//**
*
* This function prepares the USBFS component to enter low power mode. The
* interrupt on falling edge on Dp pin is configured to wakeup device when the
* host drives resume condition. The pull-up is enabled on the Dp line while
* device is in low power mode. The supported low power modes are Deep Sleep
* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP).
*
* *Note* For PSoC 4200L devices, this function should not be called before
* entering Sleep.
*
* *Note* After enter low power mode, the data which is left in the IN or OUT
* endpoint buffers is not restored after wakeup and lost. Therefore it should
* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint
* before enter low power mode.
*
* \globalvars
* USBUART_backup.enable: modified.
*
* \reentrant
* No.
*
*******************************************************************************/
void USBUART_Suspend(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if (0u != (USBUART_CR0_REG & USBUART_CR0_ENABLE))
{
/* USB block is enabled. */
USBUART_backup.enableState = 1u;
#if (USBUART_EP_MANAGEMENT_DMA)
USBUART_Stop_DMA(USBUART_MAX_EP);
#endif /* (USBUART_EP_MANAGEMENT_DMA) */
#if (CY_PSOC4)
/* Suspend enter sequence. */
USBUART_POWER_CTRL_REG |= (USBUART_POWER_CTRL_SUSPEND |
USBUART_POWER_CTRL_SUSPEND_DEL);
/* Store state of USB regulator and disable it. */
USBUART_backup.mode = (uint8) (USBUART_CR1_REG & USBUART_CR1_REG_ENABLE);
USBUART_CR1_REG &= (uint32) ~USBUART_CR1_REG_ENABLE;
/* Store SIE interrupt sources. Valid bits are 0 - 4. */
USBUART_backup.intrSeiMask = (uint8) USBUART_INTR_SIE_MASK_REG;
#else
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */
USBUART_USBIO_CR0_REG &= (uint8) ~USBUART_USBIO_CR0_TEN;
CyDelayUs(USBUART_WAIT_REG_STABILITY_50NS); /*~50ns delay. */
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */
USBUART_PM_USB_CR0_REG &= (uint8) ~(USBUART_PM_USB_CR0_PD_N |
USBUART_PM_USB_CR0_PD_PULLUP_N);
/* Disable the SIE. */
USBUART_CR0_REG &= (uint8) ~USBUART_CR0_ENABLE;
CyDelayUs(USBUART_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */
/* Store mode and disable VRegulator. */
USBUART_backup.mode = (uint8) (USBUART_CR1_REG & USBUART_CR1_REG_ENABLE);
USBUART_CR1_REG &= (uint8) ~USBUART_CR1_REG_ENABLE;
CyDelayUs(USBUART_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG &= (uint8) ~USBUART_PM_USB_CR0_REF_EN;
/* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */
USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;
/* Disable USBFS block. */
/* Clear power active and standby mode templates: disable USB block. */
USBUART_PM_ACT_CFG_REG &= (uint8) ~USBUART_PM_ACT_EN_FSUSB;
USBUART_PM_STBY_CFG_REG &= (uint8) ~USBUART_PM_STBY_EN_FSUSB;
CyDelayUs(USBUART_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */
#endif /* (CY_PSOC4) */
}
else
{
USBUART_backup.enableState = 0u;
}
CyExitCriticalSection(enableInterrupts);
#if (USBUART_DP_ISR_ACTIVE)
/* Clear active mode Dp interrupt source history. */
(void) USBUART_Dp_ClearInterrupt();
CyIntClearPending(USBUART_DP_INTC_VECT_NUM);
CyIntEnable (USBUART_DP_INTC_VECT_NUM);
#endif /* (USBUART_DP_ISR_ACTIVE). */
}
