void Peripherals_Init(void)
{
#ifdef NVIC_AUTOINIT
NVIC_Init();
#endif /* NVIC_AUTOINIT */
#ifdef SIM_AUTOINIT
SIM_Init();
#endif /* SIM_AUTOINIT */
#ifdef MCM_AUTOINIT
MCM_Init();
#endif /* MCM_AUTOINIT */
#ifdef PMC_AUTOINIT
PMC_Init();
#endif /* PMC_AUTOINIT */
#ifdef PORTA_AUTOINIT
PORTA_Init();
#endif /* PORTA_AUTOINIT */
#ifdef PORTB_AUTOINIT
PORTB_Init();
#endif /* PORTB_AUTOINIT */
#ifdef PORTC_AUTOINIT
PORTC_Init();
#endif /* PORTC_AUTOINIT */
#ifdef PORTD_AUTOINIT
PORTD_Init();
#endif /* PORTD_AUTOINIT */
#ifdef PORTE_AUTOINIT
PORTE_Init();
#endif /* PORTE_AUTOINIT */
#ifdef ADC0_AUTOINIT
ADC0_Init();
#endif /* ADC0_AUTOINIT */
#ifdef ADC1_AUTOINIT
ADC1_Init();
#endif /* ADC1_AUTOINIT */
#ifdef AIPS0_AUTOINIT
AIPS0_Init();
#endif /* AIPS0_AUTOINIT */
#ifdef CMP0_AUTOINIT
CMP0_Init();
#endif /* CMP0_AUTOINIT */
#ifdef CMP1_AUTOINIT
CMP1_Init();
#endif /* CMP1_AUTOINIT */
#ifdef CRC_AUTOINIT
CRC_Init();
#endif /* CRC_AUTOINIT */
#ifdef DAC0_AUTOINIT
DAC0_Init();
#endif /* DAC0_AUTOINIT */
#ifdef DAC1_AUTOINIT
DAC1_Init();
#endif /* DAC1_AUTOINIT */
#ifdef DMAMUX_AUTOINIT
DMAMUX_Init();
#endif /* DMAMUX_AUTOINIT */
#ifdef DMA_AUTOINIT
DMA_Init();
#endif /* DMA_AUTOINIT */
#ifdef EWM_AUTOINIT
EWM_Init();
#endif /* EWM_AUTOINIT */
#ifdef FB_AUTOINIT
FB_Init();
#endif /* FB_AUTOINIT */
#ifdef FMC_AUTOINIT
FMC_Init();
#endif /* FMC_AUTOINIT */
#ifdef FTFA_AUTOINIT
FTFA_Init();
#endif /* FTFA_AUTOINIT */
#ifdef FTM0_AUTOINIT
FTM0_Init();
#endif /* FTM0_AUTOINIT */
#ifdef FTM1_AUTOINIT
FTM1_Init();
#endif /* FTM1_AUTOINIT */
#ifdef FTM2_AUTOINIT
FTM2_Init();
#endif /* FTM2_AUTOINIT */
#ifdef FTM3_AUTOINIT
FTM3_Init();
#endif /* FTM3_AUTOINIT */
#ifdef I2C0_AUTOINIT
I2C0_Init();
#endif /* I2C0_AUTOINIT */
#ifdef I2C1_AUTOINIT
I2C1_Init();
#endif /* I2C1_AUTOINIT */
#ifdef I2S0_AUTOINIT
I2S0_Init();
#endif /* I2S0_AUTOINIT */
#ifdef LLWU_AUTOINIT
LLWU_Init();
#endif /* LLWU_AUTOINIT */
#ifdef LPTMR0_AUTOINIT
LPTMR0_Init();
#endif /* LPTMR0_AUTOINIT */
#ifdef LPUART0_AUTOINIT
LPUART0_Init();
#endif /* LPUART0_AUTOINIT */
#ifdef PDB0_AUTOINIT
PDB0_Init();
#endif /* PDB0_AUTOINIT */
#ifdef PIT_AUTOINIT
PIT_Init();
#endif /* PIT_AUTOINIT */
#ifdef PTA_AUTOINIT
PTA_Init();
#endif /* PTA_AUTOINIT */
#ifdef PTB_AUTOINIT
PTB_Init();
#endif /* PTB_AUTOINIT */
#ifdef PTC_AUTOINIT
PTC_Init();
#endif /* PTC_AUTOINIT */
#ifdef PTD_AUTOINIT
PTD_Init();
#endif /* PTD_AUTOINIT */
#ifdef PTE_AUTOINIT
PTE_Init();
#endif /* PTE_AUTOINIT */
#ifdef RCM_AUTOINIT
RCM_Init();
#endif /* RCM_AUTOINIT */
#ifdef RNG_AUTOINIT
RNG_Init();
#endif /* RNG_AUTOINIT */
#ifdef RTC_AUTOINIT
RTC_Init();
#endif /* RTC_AUTOINIT */
#ifdef SMC_AUTOINIT
SMC_Init();
#endif /* SMC_AUTOINIT */
#ifdef SPI0_AUTOINIT
SPI0_Init();
#endif /* SPI0_AUTOINIT */
#ifdef SPI1_AUTOINIT
SPI1_Init();
#endif /* SPI1_AUTOINIT */
#ifdef SystemControl_AUTOINIT
SystemControl_Init();
#endif /* SystemControl_AUTOINIT */
#ifdef SysTick_AUTOINIT
SysTick_Init();
#endif /* SysTick_AUTOINIT */
#ifdef UART0_AUTOINIT
UART0_Init();
#endif /* UART0_AUTOINIT */
#ifdef UART1_AUTOINIT
UART1_Init();
#endif /* UART1_AUTOINIT */
#ifdef UART2_AUTOINIT
UART2_Init();
#endif /* UART2_AUTOINIT */
#ifdef USB0_AUTOINIT
USB0_Init();
#endif /* USB0_AUTOINIT */
#ifdef VREF_AUTOINIT
VREF_Init();
#endif /* VREF_AUTOINIT */
#ifdef WDOG_AUTOINIT
WDOG_Init();
#endif /* WDOG_AUTOINIT */
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_DMA | RST_CLK_PCLK_PORTE),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_TIMER1 | RST_CLK_PCLK_DAC),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2),ENABLE);
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Reset PORTE settings */
PORT_DeInit(MDR_PORTE);
/* Configure DAC pin: DAC1_OUT */
/* Configure PORTE pin 9 */
PORT_InitStructure.PORT_Pin = PORT_Pin_2;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_MODE = PORT_MODE_ANALOG;
PORT_Init(MDR_PORTE, &PORT_InitStructure);
/* DMA Configuration */
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)Sine12bit;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_DAC->DAC1_DATA));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_PriCtrlStr.DMA_CycleSize = 32;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Alternate Control Data */
DMA_AltCtrlStr.DMA_SourceBaseAddr = (uint32_t)Sine12bit;
DMA_AltCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_DAC->DAC1_DATA));
DMA_AltCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_AltCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_AltCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_AltCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_AltCtrlStr.DMA_CycleSize = 32;
DMA_AltCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_AltCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_AltCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_AltCtrlData = &DMA_AltCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel TIM1*/
DMA_Init(DMA_Channel_REQ_TIM1, &DMA_InitStr);
/* Enable dma_req or dma_sreq to generate DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = DMA_SELECT(DMA_Channel_REQ_TIM1);
MDR_DMA->CHNL_USEBURST_CLR = DMA_SELECT(DMA_Channel_REQ_TIM1);
/* Enable DMA_Channel_TIM1 */
DMA_Cmd(DMA_Channel_REQ_TIM1, ENABLE);
/* ADC Configuration */
/* Reset all ADC settings */
DAC_DeInit();
/* DAC channel1 Configuration */
DAC1_Init(DAC1_AVCC);
/* DAC channel1 enable */
DAC1_Cmd(ENABLE);
/* TIMER1 Configuration */
/* Time base configuration */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
sTIM_CntInit.TIMER_Prescaler = 0;
sTIM_CntInit.TIMER_Period = 0xFF;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
/* Enable DMA for TIMER1 */
TIMER_DMACmd(MDR_TIMER1, TIMER_STATUS_CNT_ARR, TIMER_DMA_Channel0, ENABLE);
/* TIMER1 enable counter */
TIMER_Cmd(MDR_TIMER1,ENABLE);
/* Enable DMA IRQ */
NVIC_EnableIRQ(DMA_IRQn);
/* Infinite loop */
while(1)
{
}
}
