void smt_free_mbuf(struct s_smc *smc, SMbuf *mb)
{
if (mb) {
mb->sm_use_count-- ;
DB_GEN("free_mbuf: sm_use_count = %d",mb->sm_use_count,0,3) ;
/*
* If the use_count is != zero the MBuf is queued
* more than once and must not queued into the
* free MBuf queue
*/
if (!mb->sm_use_count) {
DB_GEN("free SMbuf: mb = %x",(void *)mb,0,3) ;
#ifndef COMMON_MB_POOL
mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
smc->os.hwm.mbuf_pool.mb_free = mb ;
#else
mb->sm_next = mb_free ;
mb_free = mb ;
#endif
}
}
else
SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
}
static u_long init_descr_ring(struct s_smc *smc,
union s_fp_descr volatile *start,
int count)
{
int i ;
union s_fp_descr volatile *d1 ;
union s_fp_descr volatile *d2 ;
u_long phys ;
DB_GEN("descr ring starts at = %x ",(void *)start,0,3) ;
for (i=count-1, d1=start; i ; i--) {
d2 = d1 ;
d1++ ; /* descr is owned by the host */
d2->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
d2->r.rxd_next = &d1->r ;
phys = mac_drv_virt2phys(smc,(void *)d1) ;
d2->r.rxd_nrdadr = cpu_to_le32(phys) ;
}
DB_GEN("descr ring ends at = %x ",(void *)d1,0,3) ;
d1->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
d1->r.rxd_next = &start->r ;
phys = mac_drv_virt2phys(smc,(void *)start) ;
d1->r.rxd_nrdadr = cpu_to_le32(phys) ;
for (i=count, d1=start; i ; i--) {
DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
d1++;
}
return(phys) ;
}
/**
* \brief TWD get FEM type
* *
* \param Handle - handle to object
* \return uint8
*
* \par Description
* The function return the Front end module that was read frm FW register *
* \sa
*/
TI_UINT8 TWD_GetFEMType (TI_HANDLE hTWD)
{
TTwd *pTWD = (TTwd *)hTWD;
IniFileGeneralParam *pGenParams = &DB_GEN(pTWD->hCmdBld);
return pGenParams->TXBiPFEMManufacturer;
}
static void init_txd_ring(struct s_smc *smc)
{
struct s_smt_fp_txd volatile *ds ;
struct s_smt_tx_queue *queue ;
u_long phys ;
/*
* initialize the transmit descriptors
*/
ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
queue = smc->hw.fp.tx[QUEUE_A0] ;
DB_GEN("Init async TxD ring, %d TxDs ",HWM_ASYNC_TXD_COUNT,0,3) ;
(void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
HWM_ASYNC_TXD_COUNT) ;
phys = le32_to_cpu(ds->txd_ntdadr) ;
ds++ ;
queue->tx_curr_put = queue->tx_curr_get = ds ;
ds-- ;
queue->tx_free = HWM_ASYNC_TXD_COUNT ;
queue->tx_used = 0 ;
outpd(ADDR(B5_XA_DA),phys) ;
ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
queue = smc->hw.fp.tx[QUEUE_S] ;
DB_GEN("Init sync TxD ring, %d TxDs ",HWM_SYNC_TXD_COUNT,0,3) ;
(void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
HWM_SYNC_TXD_COUNT) ;
phys = le32_to_cpu(ds->txd_ntdadr) ;
ds++ ;
queue->tx_curr_put = queue->tx_curr_get = ds ;
queue->tx_free = HWM_SYNC_TXD_COUNT ;
queue->tx_used = 0 ;
outpd(ADDR(B5_XS_DA),phys) ;
}
SMbuf *smt_get_mbuf(struct s_smc *smc)
{
register SMbuf *mb ;
#ifndef COMMON_MB_POOL
mb = smc->os.hwm.mbuf_pool.mb_free ;
#else
mb = mb_free ;
#endif
if (mb) {
#ifndef COMMON_MB_POOL
smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
#else
mb_free = mb->sm_next ;
#endif
mb->sm_off = 8 ;
mb->sm_use_count = 1 ;
}
DB_GEN("get SMbuf: mb = %x",(void *)mb,0,3) ;
return (mb) ; /* May be NULL */
}
static void init_rxd_ring(struct s_smc *smc)
{
struct s_smt_fp_rxd volatile *ds ;
struct s_smt_rx_queue *queue ;
u_long phys ;
/*
* initialize the receive descriptors
*/
ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
queue = smc->hw.fp.rx[QUEUE_R1] ;
DB_GEN("Init RxD ring, %d RxDs ",SMT_R1_RXD_COUNT,0,3) ;
(void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
SMT_R1_RXD_COUNT) ;
phys = le32_to_cpu(ds->rxd_nrdadr) ;
ds++ ;
queue->rx_curr_put = queue->rx_curr_get = ds ;
queue->rx_free = SMT_R1_RXD_COUNT ;
queue->rx_used = 0 ;
outpd(ADDR(B4_R1_DA),phys) ;
}
void fddi_isr(struct s_smc *smc)
{
u_long is ; /* ISR source */
u_short stu, stl ;
SMbuf *mb ;
#ifdef USE_BREAK_ISR
int force_irq ;
#endif
#ifdef ODI2
if (smc->os.hwm.rx_break) {
mac_drv_fill_rxd(smc) ;
if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
smc->os.hwm.rx_break = 0 ;
process_receive(smc) ;
}
else {
smc->os.hwm.detec_count = 0 ;
smt_force_irq(smc) ;
}
}
#endif
smc->os.hwm.isr_flag = TRUE ;
#ifdef USE_BREAK_ISR
force_irq = TRUE ;
if (smc->os.hwm.leave_isr) {
smc->os.hwm.leave_isr = FALSE ;
process_receive(smc) ;
}
#endif
while ((is = GET_ISR() & ISR_MASK)) {
NDD_TRACE("CH0B",is,0,0) ;
DB_GEN("ISA = 0x%x",is,0,7) ;
if (is & IMASK_SLOW) {
NDD_TRACE("CH1b",is,0,0) ;
if (is & IS_PLINT1) { /* PLC1 */
plc1_irq(smc) ;
}
if (is & IS_PLINT2) { /* PLC2 */
plc2_irq(smc) ;
}
if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
stu = inpw(FM_A(FM_ST1U)) ;
stl = inpw(FM_A(FM_ST1L)) ;
DB_GEN("Slow transmit complete",0,0,6) ;
mac1_irq(smc,stu,stl) ;
}
if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
stu= inpw(FM_A(FM_ST2U)) ;
stl= inpw(FM_A(FM_ST2L)) ;
DB_GEN("Slow receive complete",0,0,6) ;
DB_GEN("stl = %x : stu = %x",stl,stu,7) ;
mac2_irq(smc,stu,stl) ;
}
if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
stu= inpw(FM_A(FM_ST3U)) ;
stl= inpw(FM_A(FM_ST3L)) ;
DB_GEN("FORMAC Mode Register 3",0,0,6) ;
mac3_irq(smc,stu,stl) ;
}
if (is & IS_TIMINT) { /* Timer 82C54-2 */
timer_irq(smc) ;
#ifdef NDIS_OS2
force_irq_pending = 0 ;
#endif
/*
* out of RxD detection
*/
if (++smc->os.hwm.detec_count > 4) {
/*
* check out of RxD condition
*/
process_receive(smc) ;
}
}
if (is & IS_TOKEN) { /* Restricted Token Monitor */
rtm_irq(smc) ;
}
if (is & IS_R1_P) { /* Parity error rx queue 1 */
/* clear IRQ */
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
}
if (is & IS_R1_C) { /* Encoding error rx queue 1 */
/* clear IRQ */
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
}
if (is & IS_XA_C) { /* Encoding error async tx q */
/* clear IRQ */
outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
}
if (is & IS_XS_C) { /* Encoding error sync tx q */
/* clear IRQ */
outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
}
}
/*
* Fast Tx complete Async/Sync Queue (BMU service)
*/
if (is & (IS_XS_F|IS_XA_F)) {
DB_GEN("Fast tx complete queue",0,0,6) ;
/*
* clear IRQ, Note: no IRQ is lost, because
* we always service both queues
*/
outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
mac_drv_clear_txd(smc) ;
llc_restart_tx(smc) ;
}
/*
* Fast Rx Complete (BMU service)
*/
if (is & IS_R1_F) {
DB_GEN("Fast receive complete",0,0,6) ;
/* clear IRQ */
#ifndef USE_BREAK_ISR
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
process_receive(smc) ;
#else
process_receive(smc) ;
if (smc->os.hwm.leave_isr) {
force_irq = FALSE ;
} else {
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
process_receive(smc) ;
}
#endif
}
#ifndef NDIS_OS2
while ((mb = get_llc_rx(smc))) {
smt_to_llc(smc,mb) ;
}
#else
if (offDepth)
post_proc() ;
while (!offDepth && (mb = get_llc_rx(smc))) {
smt_to_llc(smc,mb) ;
}
if (!offDepth && smc->os.hwm.rx_break) {
process_receive(smc) ;
}
#endif
if (smc->q.ev_get != smc->q.ev_put) {
NDD_TRACE("CH2a",0,0,0) ;
ev_dispatcher(smc) ;
}
#ifdef NDIS_OS2
post_proc() ;
if (offDepth) { /* leave fddi_isr because */
break ; /* indications not allowed */
}
#endif
#ifdef USE_BREAK_ISR
if (smc->os.hwm.leave_isr) {
break ; /* leave fddi_isr */
}
#endif
/* NOTE: when the isr is left, no rx is pending */
} /* end of interrupt source polling loop */
#ifdef USE_BREAK_ISR
if (smc->os.hwm.leave_isr && force_irq) {
smt_force_irq(smc) ;
}
#endif
smc->os.hwm.isr_flag = FALSE ;
NDD_TRACE("CH0E",0,0,0) ;
}
void init_fddi_driver(struct s_smc *smc, u_char *mac_addr)
{
SMbuf *mb ;
int i ;
init_board(smc,mac_addr) ;
(void)init_fplus(smc) ;
/*
* initialize the SMbufs for the SMT
*/
#ifndef COMMON_MB_POOL
mb = smc->os.hwm.mbuf_pool.mb_start ;
smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
for (i = 0; i < MAX_MBUF; i++) {
mb->sm_use_count = 1 ;
smt_free_mbuf(smc,mb) ;
mb++ ;
}
#else
mb = mb_start ;
if (!mb_init) {
mb_free = 0 ;
for (i = 0; i < MAX_MBUF; i++) {
mb->sm_use_count = 1 ;
smt_free_mbuf(smc,mb) ;
mb++ ;
}
mb_init = TRUE ;
}
#endif
/*
* initialize the other variables
*/
smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
smc->os.hwm.pass_llc_promisc = TRUE ;
smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
smc->os.hwm.detec_count = 0 ;
smc->os.hwm.rx_break = 0 ;
smc->os.hwm.rx_len_error = 0 ;
smc->os.hwm.isr_flag = FALSE ;
/*
* make sure that the start pointer is 16 byte aligned
*/
i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
if (i != 16) {
DB_GEN("i = %d",i,0,3) ;
smc->os.hwm.descr_p = (union s_fp_descr volatile *)
((char *)smc->os.hwm.descr_p+i) ;
}
DB_GEN("pt to descr area = %x",(void *)smc->os.hwm.descr_p,0,3) ;
init_txd_ring(smc) ;
init_rxd_ring(smc) ;
mac_drv_fill_rxd(smc) ;
init_plc(smc) ;
}
TI_STATUS TWD_SetDefaults (TI_HANDLE hTWD, TTwdInitParams *pInitParams)
{
TTwd *pTWD = (TTwd *)hTWD;
TWlanParams *pWlanParams = &DB_WLAN(pTWD->hCmdBld);
TKeepAliveList *pKlvParams = &DB_KLV(pTWD->hCmdBld);
IniFileRadioParam *pRadioParams = &DB_RADIO(pTWD->hCmdBld);
IniFileGeneralParam *pGenParams = &DB_GEN(pTWD->hCmdBld);
TRateMngParams *pRateMngParams = &DB_RM(pTWD->hCmdBld);
TDmaParams *pDmaParams = &DB_DMA(pTWD->hCmdBld);
TI_UINT32 k, uIndex;
int iParam;
pTWD->bRecoveryEnabled = pInitParams->tGeneral.halCtrlRecoveryEnable;
pWlanParams->PacketDetectionThreshold = pInitParams->tGeneral.packetDetectionThreshold;
pWlanParams->qosNullDataTemplateSize = pInitParams->tGeneral.qosNullDataTemplateSize;
pWlanParams->PsPollTemplateSize = pInitParams->tGeneral.PsPollTemplateSize;
pWlanParams->probeResponseTemplateSize = pInitParams->tGeneral.probeResponseTemplateSize;
pWlanParams->probeRequestTemplateSize = pInitParams->tGeneral.probeRequestTemplateSize;
pWlanParams->beaconTemplateSize = pInitParams->tGeneral.beaconTemplateSize;
pWlanParams->nullTemplateSize = pInitParams->tGeneral.nullTemplateSize;
pWlanParams->disconnTemplateSize = pInitParams->tGeneral.disconnTemplateSize;
pWlanParams->ArpRspTemplateSize = pInitParams->tGeneral.ArpRspTemplateSize;
/* Beacon broadcast options */
pWlanParams->BcnBrcOptions.BeaconRxTimeout = pInitParams->tGeneral.BeaconRxTimeout;
pWlanParams->BcnBrcOptions.BroadcastRxTimeout = pInitParams->tGeneral.BroadcastRxTimeout;
pWlanParams->BcnBrcOptions.RxBroadcastInPs = pInitParams->tGeneral.RxBroadcastInPs;
pWlanParams->ConsecutivePsPollDeliveryFailureThreshold = pInitParams->tGeneral.ConsecutivePsPollDeliveryFailureThreshold;
pWlanParams->RxDisableBroadcast = pInitParams->tGeneral.halCtrlRxDisableBroadcast;
pWlanParams->calibrationChannel2_4 = pInitParams->tGeneral.halCtrlCalibrationChannel2_4;
pWlanParams->calibrationChannel5_0 = pInitParams->tGeneral.halCtrlCalibrationChannel5_0;
/* Not used but need by Palau */
pWlanParams->RtsThreshold = pInitParams->tGeneral.halCtrlRtsThreshold;
pWlanParams->CtsToSelf = CTS_TO_SELF_DISABLE;
pWlanParams->WiFiWmmPS = pInitParams->tGeneral.WiFiWmmPS;
pWlanParams->MaxTxMsduLifetime = pInitParams->tGeneral.halCtrlMaxTxMsduLifetime;
pWlanParams->MaxRxMsduLifetime = pInitParams->tGeneral.halCtrlMaxRxMsduLifetime;
pWlanParams->rxTimeOut.psPoll = pInitParams->tGeneral.rxTimeOut.psPoll;
pWlanParams->rxTimeOut.UPSD = pInitParams->tGeneral.rxTimeOut.UPSD;
/* RSSI/SNR Weights for Average calculations */
pWlanParams->tRssiSnrWeights.rssiBeaconAverageWeight = pInitParams->tGeneral.uRssiBeaconAverageWeight;
pWlanParams->tRssiSnrWeights.rssiPacketAverageWeight = pInitParams->tGeneral.uRssiPacketAverageWeight;
pWlanParams->tRssiSnrWeights.snrBeaconAverageWeight = pInitParams->tGeneral.uSnrBeaconAverageWeight ;
pWlanParams->tRssiSnrWeights.snrPacketAverageWeight = pInitParams->tGeneral.uSnrPacketAverageWeight ;
/* PM config params */
pWlanParams->uHostClkSettlingTime = pInitParams->tGeneral.uHostClkSettlingTime;
pWlanParams->uHostFastWakeupSupport = pInitParams->tGeneral.uHostFastWakeupSupport;
/* No used */
pWlanParams->FragmentThreshold = pInitParams->tGeneral.halCtrlFragThreshold;
pWlanParams->ListenInterval = (TI_UINT8)pInitParams->tGeneral.halCtrlListenInterval;
pWlanParams->RateFallback = pInitParams->tGeneral.halCtrlRateFallbackRetry;
pWlanParams->MacClock = pInitParams->tGeneral.halCtrlMacClock;
pWlanParams->ArmClock = pInitParams->tGeneral.halCtrlArmClock;
/* Data interrupts pacing */
pWlanParams->TxCompletePacingThreshold = pInitParams->tGeneral.TxCompletePacingThreshold;
pWlanParams->TxCompletePacingTimeout = pInitParams->tGeneral.TxCompletePacingTimeout;
pWlanParams->RxIntrPacingThreshold = pInitParams->tGeneral.RxIntrPacingThreshold;
pWlanParams->RxIntrPacingTimeout = pInitParams->tGeneral.RxIntrPacingTimeout;
/* Number of Rx mem-blocks to allocate in FW */
pDmaParams->NumRxBlocks = pInitParams->tGeneral.uRxMemBlksNum;
/* Configure ARP IP */
pWlanParams->arpFilterType = pInitParams->tArpIpFilter.filterType;
IP_COPY (pWlanParams->arp_IP_addr, pInitParams->tArpIpFilter.addr);
/* Configure address group */
pWlanParams->numGroupAddrs = pInitParams->tMacAddrFilter.numOfMacAddresses;
pWlanParams->isMacAddrFilteringnabled = pInitParams->tMacAddrFilter.isFilterEnabled;
for (k = 0; k < pWlanParams->numGroupAddrs; k++)
{
MAC_COPY (pWlanParams->aGroupAddr[k], pInitParams->tMacAddrFilter.macAddrTable[k]);
}
/* CoexActivity Table */
pWlanParams->tWlanParamsCoexActivityTable.numOfElements = 0;
for (iParam=0; iParam < (int)pInitParams->tGeneral.halCoexActivityTable.numOfElements; iParam++)
{
TCoexActivity *pSaveCoex = &pWlanParams->tWlanParamsCoexActivityTable.entry[0];
TCoexActivity *pParmCoex = &pInitParams->tGeneral.halCoexActivityTable.entry[0];
int i, saveIndex;
/* Check if to overwrite existing entry or put on last index */
for (i=0; i<iParam; i++)
{
if ((pSaveCoex[i].activityId == pParmCoex[iParam].activityId) && (pSaveCoex[i].coexIp == pParmCoex[iParam].coexIp))
{
break;
}
}
if (i == iParam)
{
/* new entry */
saveIndex = pWlanParams->tWlanParamsCoexActivityTable.numOfElements;
pWlanParams->tWlanParamsCoexActivityTable.numOfElements++;
}
else
{
/* overwrite existing */
saveIndex = i;
}
pSaveCoex[saveIndex].coexIp = pParmCoex[iParam].coexIp;
pSaveCoex[saveIndex].activityId = pParmCoex[iParam].activityId;
pSaveCoex[saveIndex].defaultPriority = pParmCoex[iParam].defaultPriority;
pSaveCoex[saveIndex].raisedPriority = pParmCoex[iParam].raisedPriority;
pSaveCoex[saveIndex].minService = pParmCoex[iParam].minService;
pSaveCoex[saveIndex].maxService = pParmCoex[iParam].maxService;
}
/* configure keep-alive default mode to enabled */
pKlvParams->enaDisFlag = TI_TRUE;
for (uIndex = 0; uIndex < KLV_MAX_TMPL_NUM; uIndex++)
{
pKlvParams->keepAliveParams[ uIndex ].enaDisFlag = TI_FALSE;
}
/* Configure the TWD modules */
rxXfer_SetDefaults (pTWD->hRxXfer, pInitParams);
txXfer_SetDefaults (pTWD->hTxXfer, pInitParams);
txHwQueue_Config (pTWD->hTxHwQueue, pInitParams);
MacServices_config (pTWD->hMacServices, pInitParams);
/*
* 802.11n
*/
pWlanParams->tTwdHtCapabilities.b11nEnable = pInitParams->tGeneral.b11nEnable;
/* Configure HT capabilities setting */
pWlanParams->tTwdHtCapabilities.uChannelWidth = CHANNEL_WIDTH_20MHZ;
pWlanParams->tTwdHtCapabilities.uRxSTBC = RXSTBC_SUPPORTED_ONE_SPATIAL_STREAM;
pWlanParams->tTwdHtCapabilities.uMaxAMSDU = MAX_MSDU_3839_OCTETS;
pWlanParams->tTwdHtCapabilities.uMaxAMPDU = MAX_MPDU_8191_OCTETS;
pWlanParams->tTwdHtCapabilities.uAMPDUSpacing = AMPDU_SPC_8_MICROSECONDS;
pWlanParams->tTwdHtCapabilities.aRxMCS[0] = (MCS_SUPPORT_MCS_0 |
MCS_SUPPORT_MCS_1 |
MCS_SUPPORT_MCS_2 |
MCS_SUPPORT_MCS_3 |
MCS_SUPPORT_MCS_4 |
MCS_SUPPORT_MCS_5 |
MCS_SUPPORT_MCS_6 |
MCS_SUPPORT_MCS_7);
os_memoryZero (pTWD->hOs, pWlanParams->tTwdHtCapabilities.aRxMCS + 1, RX_TX_MCS_BITMASK_SIZE - 1);
pWlanParams->tTwdHtCapabilities.aTxMCS[0] = (MCS_SUPPORT_MCS_0 |
MCS_SUPPORT_MCS_1 |
MCS_SUPPORT_MCS_2 |
MCS_SUPPORT_MCS_3 |
MCS_SUPPORT_MCS_4 |
MCS_SUPPORT_MCS_5 |
MCS_SUPPORT_MCS_6 |
MCS_SUPPORT_MCS_7);
os_memoryZero (pTWD->hOs, pWlanParams->tTwdHtCapabilities.aTxMCS + 1, RX_TX_MCS_BITMASK_SIZE - 1);
pWlanParams->tTwdHtCapabilities.uRxMaxDataRate = MCS_HIGHEST_SUPPORTED_RECEPTION_DATA_RATE_IN_MBIT_S;
pWlanParams->tTwdHtCapabilities.uPCOTransTime = PCO_TRANS_TIME_NO_TRANSITION;
pWlanParams->tTwdHtCapabilities.uHTCapabilitiesBitMask = (CAP_BIT_MASK_GREENFIELD_FRAME_FORMAT |
CAP_BIT_MASK_SHORT_GI_FOR_20MHZ_PACKETS);
pWlanParams->tTwdHtCapabilities.uMCSFeedback = MCS_FEEDBACK_NO;
os_memoryCopy(pTWD->hOs, (void*)pRadioParams, (void*)&pInitParams->tIniFileRadioParams, sizeof(IniFileRadioParam));
os_memoryCopy(pTWD->hOs, (void*)pGenParams, (void*)&pInitParams->tPlatformGenParams, sizeof(IniFileGeneralParam));
os_memoryCopy (pTWD->hOs,
(void*)&(pWlanParams->tFmCoexParams),
(void*)&(pInitParams->tGeneral.tFmCoexParams),
sizeof(TFmCoexParams));
/* Rate management params */
pRateMngParams->rateMngParams.InverseCuriosityFactor = pInitParams->tRateMngParams.InverseCuriosityFactor;
pRateMngParams->rateMngParams.MaxPer = pInitParams->tRateMngParams.MaxPer;
pRateMngParams->rateMngParams.PerAdd = pInitParams->tRateMngParams.PerAdd;
pRateMngParams->rateMngParams.PerAddShift = pInitParams->tRateMngParams.PerAddShift;
pRateMngParams->rateMngParams.PerAlphaShift = pInitParams->tRateMngParams.PerAlphaShift;
pRateMngParams->rateMngParams.PerBeta1Shift = pInitParams->tRateMngParams.PerBeta1Shift;
pRateMngParams->rateMngParams.PerBeta2Shift = pInitParams->tRateMngParams.PerBeta2Shift;
pRateMngParams->rateMngParams.PerTh1 = pInitParams->tRateMngParams.PerTh1;
pRateMngParams->rateMngParams.PerTh2 = pInitParams->tRateMngParams.PerTh2;
pRateMngParams->rateMngParams.RateCheckDown = pInitParams->tRateMngParams.RateCheckDown;
pRateMngParams->rateMngParams.RateCheckUp = pInitParams->tRateMngParams.RateCheckUp;
pRateMngParams->rateMngParams.RateRetryScore = pInitParams->tRateMngParams.RateRetryScore;
pRateMngParams->rateMngParams.TxFailHighTh = pInitParams->tRateMngParams.TxFailHighTh;
pRateMngParams->rateMngParams.TxFailLowTh = pInitParams->tRateMngParams.TxFailLowTh;
/* RATE_MNG_MAX_RETRY_POLICY_PARAMS_LEN */
for (uIndex = 0; uIndex < 13; uIndex++)
{
pRateMngParams->rateMngParams.RateRetryPolicy[uIndex] = pInitParams->tRateMngParams.RateRetryPolicy[uIndex];
}
/* DCO Itrim params */
pWlanParams->dcoItrimEnabled = pInitParams->tDcoItrimParams.enable;
pWlanParams->dcoItrimModerationTimeoutUsec = pInitParams->tDcoItrimParams.moderationTimeoutUsec;
return TI_OK;
}
