C++ (Cpp) DCRN_UIC_SR Examples

Example #1

static void __init ppc4xx_pic_impl_init(void)
{
    /* Enable cascade interrupt in UIC0 */
    ppc_cached_irq_mask[0] |= UIC0_UIC1NC;
    mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
    mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
}

Example #2

File: ppc4xx_pic.c Project: sarnobat/knoppix

static void
ppc405_uic_end(unsigned int irq)
{
	int bit, word;
	unsigned int tr_bits;

	bit = irq & 0x1f;
	word = irq >> 5;

#ifdef UIC_DEBUG
	printk("ppc405_uic_end - irq %d word %d bit 0x%x\n", irq, word, bit);
#endif

	switch (word) {
	case 0:
		tr_bits = mfdcr(DCRN_UIC_TR(UIC0));
		break;
	case 1:
		tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
		break;
	}

	if ((tr_bits & (1 << (31 - bit))) == 0) {
		/* level trigger */
		switch (word) {
		case 0:
			mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit));
			break;
		case 1:
			mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
			break;
		}
	}

	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
		ppc_cached_irq_mask[word] |= 1 << (31 - bit);
		switch (word) {
		case 0:
			mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
			break;
		case 1:
			mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
			break;
		}
	}
}

Example #3

static void __init ppc4xx_pic_impl_init(void)
{
    /* Configure Base UIC */
    mtdcr(DCRN_UIC_CR(UICB), 0);
    mtdcr(DCRN_UIC_TR(UICB), 0);
    mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
    mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
    mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
}

Example #4

File: ppc4xx_pic.c Project: sarnobat/knoppix

void __init
ppc4xx_pic_init(void)
{

	/*
	 * Disable all external interrupts until they are
	 * explicity requested.
	 */
	ppc_cached_irq_mask[0] = 0;
	ppc_cached_irq_mask[1] = 0;

#if defined CONFIG_403
	mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);

	ppc4xx_pic = &ppc403_aic;
	ppc_md.get_irq = ppc403_pic_get_irq;
#else
#if  (NR_UICS > 1)
	ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC);	/* enable cascading interrupt */
	mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[1]);
	mtdcr(DCRN_UIC_CR(UIC1), 0);

#endif
	mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
	mtdcr(DCRN_UIC_CR(UIC0), 0);

	if (ibm4xxPIC_InitSenses != NULL)
		ppc4xx_extpic_init();

	/* Clear any pending interrupts */
#if (NR_UICS > 1)
	mtdcr(DCRN_UIC_SR(UIC1), 0xffffffff);
#endif
	mtdcr(DCRN_UIC_SR(UIC0), 0xffffffff);

	ppc4xx_pic = &ppc405_uic;
	ppc_md.get_irq = ppc405_pic_get_irq;
#endif

}

Example #5

static void __init ppc4xx_pic_impl_init(void)
{
#if defined(CONFIG_440GX)
	/* Disable 440GP compatibility mode if it was enabled in firmware */
	SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM);
#endif
	/* Configure Base UIC */
	mtdcr(DCRN_UIC_CR(UICB), 0);
	mtdcr(DCRN_UIC_TR(UICB), 0);
	mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
	mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
	mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
}

Example #6

File: ppc4xx_pic.c Project: sarnobat/knoppix

static void
ppc405_uic_disable_and_ack(unsigned int irq)
{
	int bit, word;

	bit = irq & 0x1f;
	word = irq >> 5;

#ifdef UIC_DEBUG
	printk("ppc405_uic_disable_and_ack - irq %d word %d bit 0x%x\n", irq,
	       word, bit);
#endif
	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
	switch (word) {
	case 0:
		mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
		mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit)));
		break;
	case 1:
		mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
		mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
		break;
	}
}