void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; if (popts->registered_dimm_en) pbsp = rdimms[0]; else pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); popts->data_bus_width = 0; /* 64-bit data bus */ popts->bstopre = 0; /* enable auto precharge */ /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; /* optimize cpo for erratum A-009942 */ popts->cpo_sample = 0x61; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; /* * we use identical timing for all slots. If needed, change the code * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; */ pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* Enable ZQ calibration */ popts->zq_en = 1; /* Enable DDR hashing */ popts->addr_hash = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) fsl_ddr_setup_0v9_volt(popts); #endif popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 3) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; popts->cpo_override = pbsp->cpo_override; popts->write_data_delay = pbsp->write_data_delay; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; popts->otf_burst_chop_en = 0; popts->burst_length = DDR_BL8; /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 1; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; #ifdef CONFIG_SYS_FSL_DDR4 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ #else popts->cswl_override = DDR_CSWL_CS0; /* optimize cpo for erratum A-009942 */ popts->cpo_sample = 0x58; /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); #endif }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 2) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; pbsp = udimms[0]; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; popts->twoT_en = pbsp->force_2T; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found " "for data rate %lu MT/s\n" "Trying to use the highest speed (%u) parameters\n", ddr_freq, pbsp_highest->datarate_mhz_high); popts->cpo_override = pbsp_highest->cpo; popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->twoT_en = pbsp_highest->force_2T; } else { panic("DIMM is not supported by this board"); } found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); }