hwif->drives[0].autodma = hwif->autodma; } #define DECLARE_PIIX_DEV(name_str) \ { \ .name = name_str, \ .init_chipset = init_chipset_piix, \ .init_hwif = init_hwif_piix, \ .channels = 2, \ .autodma = AUTODMA, \ .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ .bootable = ON_BOARD, \ } static ide_pci_device_t piix_pci_info[] __devinitdata = { /* 0 */ DECLARE_PIIX_DEV("PIIXa"), /* 1 */ DECLARE_PIIX_DEV("PIIXb"), { /* 2 */ .name = "MPIIX", .init_hwif = init_hwif_piix, .channels = 2, .autodma = NODMA, .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, .bootable = ON_BOARD, }, /* 3 */ DECLARE_PIIX_DEV("PIIX3"), /* 4 */ DECLARE_PIIX_DEV("PIIX4"), /* 5 */ DECLARE_PIIX_DEV("ICH0"), /* 6 */ DECLARE_PIIX_DEV("PIIX4"),
#define DECLARE_ICH_DEV(name_str, udma) \ { \ .name = name_str, \ .init_chipset = init_chipset_ich, \ .init_hwif = init_hwif_ich, \ .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ .port_ops = &piix_port_ops, \ .host_flags = IDE_HFLAGS_PIIX, \ .pio_mask = ATA_PIO4, \ .swdma_mask = ATA_SWDMA2_ONLY, \ .mwdma_mask = ATA_MWDMA12_ONLY, \ .udma_mask = udma, \ } static const struct ide_port_info piix_pci_info[] __devinitdata = { /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */ /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */ /* 2 */ { /* * MPIIX actually has only a single IDE channel mapped to * the primary or secondary ports depending on the value * of the bit 14 of the IDETIM register at offset 0x6c */ .name = "MPIIX", .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA | IDE_HFLAGS_PIIX, .pio_mask = ATA_PIO4, /* This is a painful system best to let it self tune for now */ },