s = g_malloc0(sizeof(ParallelState));
s->irq = irq;
s->chr = chr;
s->it_shift = it_shift;
qemu_register_reset(parallel_reset, s);
memory_region_init_io(&s->iomem, ¶llel_mm_ops, s,
"parallel", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->iomem);
return true;
}
static Property parallel_isa_properties[] = {
DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
DEFINE_PROP_END_OF_LIST(),
};
static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = parallel_isa_initfn;
dc->props = parallel_isa_properties;
}
static TypeInfo parallel_isa_info = {
.name = "isa-parallel",
static void kvm_pit_realizefn(DeviceState *dev, Error **errp)
{
PITCommonState *pit = PIT_COMMON(dev);
KVMPITClass *kpc = KVM_PIT_GET_CLASS(dev);
KVMPITState *s = KVM_PIT(pit);
struct kvm_pit_config config = {
.flags = 0,
};
int ret;
if (kvm_check_extension(kvm_state, KVM_CAP_PIT2)) {
ret = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT2, &config);
} else {
ret = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
}
if (ret < 0) {
error_setg(errp, "Create kernel PIC irqchip failed: %s",
strerror(ret));
return;
}
switch (s->lost_tick_policy) {
case LOST_TICK_DELAY:
break; /* enabled by default */
case LOST_TICK_DISCARD:
if (kvm_check_extension(kvm_state, KVM_CAP_REINJECT_CONTROL)) {
struct kvm_reinject_control control = { .pit_reinject = 0 };
ret = kvm_vm_ioctl(kvm_state, KVM_REINJECT_CONTROL, &control);
if (ret < 0) {
error_setg(errp,
"Can't disable in-kernel PIT reinjection: %s",
strerror(ret));
return;
}
}
break;
default:
error_setg(errp, "Lost tick policy not supported.");
return;
}
memory_region_init_reservation(&pit->ioports, NULL, "kvm-pit", 4);
qdev_init_gpio_in(dev, kvm_pit_irq_control, 1);
qemu_add_vm_change_state_handler(kvm_pit_vm_state_change, s);
kpc->parent_realize(dev, errp);
}
static Property kvm_pit_properties[] = {
DEFINE_PROP_HEX32("iobase", PITCommonState, iobase, -1),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", KVMPITState,
lost_tick_policy, LOST_TICK_DELAY),
DEFINE_PROP_END_OF_LIST(),
};
static void kvm_pit_class_init(ObjectClass *klass, void *data)
{
KVMPITClass *kpc = KVM_PIT_CLASS(klass);
PITCommonClass *k = PIT_COMMON_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
kpc->parent_realize = dc->realize;
dc->realize = kvm_pit_realizefn;
k->set_channel_gate = kvm_pit_set_gate;
k->get_channel_info = kvm_pit_get_channel_info;
k->pre_save = kvm_pit_get;
k->post_load = kvm_pit_put;
dc->reset = kvm_pit_reset;
dc->props = kvm_pit_properties;
}
static const TypeInfo kvm_pit_info = {
.name = TYPE_KVM_I8254,
.parent = TYPE_PIT_COMMON,
.instance_size = sizeof(KVMPITState),
.class_init = kvm_pit_class_init,
.class_size = sizeof(KVMPITClass),
};
static void kvm_pit_register(void)
{
type_register_static(&kvm_pit_info);
}
type_init(kvm_pit_register)
if (s->ctl_iobase + 1 == s->data_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->comb_iomem);
} else {
if (s->ctl_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->ctl_iomem);
}
if (s->data_iobase) {
sysbus_add_io(dev, s->data_iobase, &s->data_iomem);
}
}
return 0;
}
static Property fw_cfg_properties[] = {
DEFINE_PROP_HEX32("ctl_iobase", FWCfgState, ctl_iobase, -1),
DEFINE_PROP_HEX32("data_iobase", FWCfgState, data_iobase, -1),
DEFINE_PROP_END_OF_LIST(),
};
static void fw_cfg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = fw_cfg_init1;
dc->no_user = 1;
dc->reset = fw_cfg_reset;
dc->vmsd = &vmstate_fw_cfg;
dc->props = fw_cfg_properties;
}
return 0;
}
static const VMStateDescription vmstate_isa_serial = {
.name = "serial",
.version_id = 3,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
VMSTATE_END_OF_LIST()
}
};
static Property serial_isa_properties[] = {
DEFINE_PROP_UINT32("index", ISASerialState, index, -1),
DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, -1),
DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1),
DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void serial_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = serial_isa_initfn;
dc->vmsd = &vmstate_isa_serial;
dc->props = serial_isa_properties;
}
VMSTATE_UINT8(read_reg_select, PICCommonState),
VMSTATE_UINT8(poll, PICCommonState),
VMSTATE_UINT8(special_mask, PICCommonState),
VMSTATE_UINT8(init_state, PICCommonState),
VMSTATE_UINT8(auto_eoi, PICCommonState),
VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
VMSTATE_UINT8(init4, PICCommonState),
VMSTATE_UINT8(single_mode, PICCommonState),
VMSTATE_UINT8(elcr, PICCommonState),
VMSTATE_END_OF_LIST()
}
};
static Property pic_properties_common[] = {
DEFINE_PROP_HEX32("iobase", PICCommonState, iobase, -1),
DEFINE_PROP_HEX32("elcr_addr", PICCommonState, elcr_addr, -1),
DEFINE_PROP_HEX8("elcr_mask", PICCommonState, elcr_mask, -1),
DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
DEFINE_PROP_END_OF_LIST(),
};
static void pic_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_pic_common;
dc->no_user = 1;
dc->props = pic_properties_common;
dc->realize = pic_common_realize;
}
isa_register_ioport(dev, &s->io, isa->iobase);
isa_init_irq(dev, &s->irq, isa->isairq);
qemu_macaddr_default_if_unset(&s->c.macaddr);
ne2000_reset(s);
s->nic = qemu_new_nic(&net_ne2000_isa_info, &s->c,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->c.macaddr.a);
return 0;
}
static Property ne2000_isa_properties[] = {
DEFINE_PROP_HEX32("iobase", ISANE2000State, iobase, 0x300),
DEFINE_PROP_UINT32("irq", ISANE2000State, isairq, 9),
DEFINE_NIC_PROPERTIES(ISANE2000State, ne2000.c),
DEFINE_PROP_END_OF_LIST(),
};
static void isa_ne2000_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = isa_ne2000_initfn;
dc->props = ne2000_isa_properties;
}
static TypeInfo ne2000_isa_info = {
.name = "ne2k_isa",
qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);
}
static int debugcon_isa_initfn(ISADevice *dev)
{
ISADebugconState *isa = DO_UPCAST(ISADebugconState, dev, dev);
DebugconState *s = &isa->state;
debugcon_init_core(s);
register_ioport_write(isa->iobase, 1, 1, debugcon_ioport_write, s);
register_ioport_read(isa->iobase, 1, 1, debugcon_ioport_read, s);
return 0;
}
static Property debugcon_isa_properties[] = {
DEFINE_PROP_HEX32("iobase", ISADebugconState, iobase, 0xe9),
DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr),
DEFINE_PROP_HEX32("readback", ISADebugconState, state.readback, 0xe9),
DEFINE_PROP_END_OF_LIST(),
};
static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = debugcon_isa_initfn;
dc->props = debugcon_isa_properties;
}
static TypeInfo debugcon_isa_info = {
.name = "isa-debugcon",
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int debug_exit_initfn(ISADevice *dev)
{
ISADebugExitState *isa = ISA_DEBUG_EXIT_DEVICE(dev);
memory_region_init_io(&isa->io, &debug_exit_ops, isa,
TYPE_ISA_DEBUG_EXIT_DEVICE, isa->iosize);
memory_region_add_subregion(isa_address_space_io(dev),
isa->iobase, &isa->io);
return 0;
}
static Property debug_exit_properties[] = {
DEFINE_PROP_HEX32("iobase", ISADebugExitState, iobase, 0x501),
DEFINE_PROP_HEX32("iosize", ISADebugExitState, iosize, 0x02),
DEFINE_PROP_END_OF_LIST(),
};
static void debug_exit_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = debug_exit_initfn;
dc->props = debug_exit_properties;
}
static TypeInfo debug_exit_info = {
.name = TYPE_ISA_DEBUG_EXIT_DEVICE,
.parent = TYPE_ISA_DEVICE,
s->con = graphic_console_init(&tcx24_ops, s);
} else {
/* THC 8 bit (dummy) */
memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
TCX_THC_NREGS_8);
sysbus_init_mmio(dev, &s->thc8);
s->con = graphic_console_init(&tcx_ops, s);
}
qemu_console_resize(s->con, s->width, s->height);
return 0;
}
static Property tcx_properties[] = {
DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
DEFINE_PROP_UINT16("width", TCXState, width, -1),
DEFINE_PROP_UINT16("height", TCXState, height, -1),
DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
DEFINE_PROP_END_OF_LIST(),
};
static void tcx_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = tcx_init1;
dc->reset = tcx_reset;
dc->vmsd = &vmstate_tcx;
dc->props = tcx_properties;
