} static void generic_loader_unrealize(DeviceState *dev, Error **errp) { qemu_unregister_reset_loader(generic_loader_reset, dev); } static Property generic_loader_props[] = { DEFINE_PROP_UINT64("addr", GenericLoaderState, addr, 0), DEFINE_PROP_UINT64("data", GenericLoaderState, data, 0), DEFINE_PROP_UINT8("data-len", GenericLoaderState, data_len, 0), DEFINE_PROP_BOOL("data-be", GenericLoaderState, data_be, false), DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE), DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false), DEFINE_PROP_STRING("file", GenericLoaderState, file), DEFINE_PROP_UINT16("attrs-requester-id", GenericLoaderState, attrs.requester_id, 0), DEFINE_PROP_BOOL("attrs-debug", GenericLoaderState, attrs.debug, false), DEFINE_PROP_BOOL("attrs-secure", GenericLoaderState, attrs.secure, false), DEFINE_PROP_END_OF_LIST(), }; static void generic_loader_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); /* The reset function is not registered here and is instead registered in * the realize function to allow this device to be added via the device_add * command in the QEMU monitor. * TODO: Improve the device_add functionality to allow resets to be * connected */
{ CG3State *s = CG3(d); /* Initialize palette */ memset(s->r, 0, 256); memset(s->g, 0, 256); memset(s->b, 0, 256); s->dac_state = 0; s->full_update = 1; qemu_irq_lower(s->irq); } static Property cg3_properties[] = { DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), DEFINE_PROP_UINT16("width", CG3State, width, -1), DEFINE_PROP_UINT16("height", CG3State, height, -1), DEFINE_PROP_UINT16("depth", CG3State, depth, -1), DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1), DEFINE_PROP_END_OF_LIST(), }; static void cg3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = cg3_realizefn; dc->reset = cg3_reset; dc->vmsd = &vmstate_cg3; dc->props = cg3_properties; }
static const VMStateDescription vmstate_xio3130_upstream = { .name = "xio3130-express-upstream-port", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } }; static Property xio3130_upstream_properties[] = { DEFINE_PROP_UINT8("port", PCIEPort, port, 0), DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max, PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; static void xio3130_upstream_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->is_express = 1; k->is_bridge = 1; k->config_write = xio3130_upstream_write_config; k->init = xio3130_upstream_initfn; k->exit = xio3130_upstream_exitfn; k->vendor_id = PCI_VENDOR_ID_TI; k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE); } #define PVPANIC_IOPORT_PROP "ioport" uint16_t pvpanic_port(void) { Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL); if (!o) { return 0; } return object_property_get_int(o, PVPANIC_IOPORT_PROP, NULL); } static Property pvpanic_isa_properties[] = { DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505), DEFINE_PROP_END_OF_LIST(), }; static void pvpanic_isa_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pvpanic_isa_realizefn; dc->props = pvpanic_isa_properties; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static TypeInfo pvpanic_isa_info = { .name = TYPE_ISA_PVPANIC_DEVICE, .parent = TYPE_ISA_DEVICE,
.qdev.name = "ioh3420", .qdev.desc = "Intel IOH device id 3420 PCIE Root Port", .qdev.size = sizeof(PCIESlot), .qdev.reset = ioh3420_reset, .qdev.vmsd = &vmstate_ioh3420, .is_express = 1, .is_bridge = 1, .config_write = ioh3420_write_config, .init = ioh3420_initfn, .exit = ioh3420_exitfn, .qdev.props = (Property[]) { DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), /* TODO: AER */ DEFINE_PROP_END_OF_LIST(), } }; static void ioh3420_register(void) { pci_qdev_register(&ioh3420_info); } device_init(ioh3420_register); /* * Local variables: * c-indent-level: 4
pci_config_set_prog_interface(pci_conf, 0); pci_conf[PCI_INTERRUPT_PIN] = 1; memory_region_init_io(&d->mmio, NULL, &xen_pv_mmio_ops, d, "mmio", d->size); pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, &d->mmio); return 0; } static Property xen_pv_props[] = { DEFINE_PROP_UINT16("vendor-id", XenPVDevice, vendor_id, PCI_VENDOR_ID_XEN), DEFINE_PROP_UINT16("device-id", XenPVDevice, device_id, 0xffff), DEFINE_PROP_UINT8("revision", XenPVDevice, revision, 0x01), DEFINE_PROP_UINT32("size", XenPVDevice, size, 0x400000), DEFINE_PROP_END_OF_LIST() }; static void xen_pv_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = xen_pv_init; k->class_id = PCI_CLASS_SYSTEM_OTHER; dc->desc = "Xen PV Device"; dc->props = xen_pv_props;
.version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } }; static Property xio3130_downstream_properties[] = { DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("aer_log_max", PCIESlot, port.br.dev.exp.aer_log.log_max, PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; static void xio3130_downstream_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->is_express = 1; k->is_bridge = 1; k->config_write = xio3130_downstream_write_config; k->init = xio3130_downstream_initfn;
break; case I2C_FINISH: case I2C_NACK: s->state = IDEAL; break; } } static int si57x_init(I2CSlave *i2c) { /* Nothing to do */ return 0; } static Property si57x_properties[] = { DEFINE_PROP_UINT16("temperature-stability", Si57xState, temp_stab, TEMP_STAB_50PPM), DEFINE_PROP_END_OF_LIST(), }; static void si57x_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); k->init = si57x_init; k->event = si57x_event; k->recv = si57x_rx; k->send = si57x_tx; dc->props = si57x_properties; dc->reset = si57x_reset; }
qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1); } static const VMStateDescription vmstate_or_irq = { .name = TYPE_OR_IRQ, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_BOOL_ARRAY(levels, qemu_or_irq, MAX_OR_LINES), VMSTATE_END_OF_LIST(), } }; static Property or_irq_properties[] = { DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1), DEFINE_PROP_END_OF_LIST(), }; static void or_irq_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = or_irq_reset; dc->props = or_irq_properties; dc->realize = or_irq_realize; dc->vmsd = &vmstate_or_irq; /* Reason: Needs to be wired up to work, e.g. see stm32f205_soc.c */ dc->cannot_instantiate_with_device_add_yet = true; }