static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
{
struct dib3000_state *state = fe->demodulator_priv;
if (onoff) {
wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
} else {
wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
}
return 0;
}
static int dib3000mb_set_frontend(struct dvb_frontend* fe,
struct dvb_frontend_parameters *fep, int tuner)
{
struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
fe_code_rate_t fe_cr = FEC_NONE;
int search_state,seq;
if (tuner) {
wr(DIB3000MB_REG_TUNER,
DIB3000_TUNER_WRITE_ENABLE(state->config.pll_addr));
state->config.pll_set(fe, fep);
wr(DIB3000MB_REG_TUNER,
DIB3000_TUNER_WRITE_DISABLE(state->config.pll_addr));
deb_setf("bandwidth: ");
switch (ofdm->bandwidth) {
case BANDWIDTH_8_MHZ:
deb_setf("8 MHz\n");
wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
break;
case BANDWIDTH_7_MHZ:
deb_setf("7 MHz\n");
wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[1]);
wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_7mhz);
break;
case BANDWIDTH_6_MHZ:
deb_setf("6 MHz\n");
wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[0]);
wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_6mhz);
break;
case BANDWIDTH_AUTO:
return -EOPNOTSUPP;
default:
err("unkown bandwidth value.");
return -EINVAL;
}
}
wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
deb_setf("transmission mode: ");
switch (ofdm->transmission_mode) {
case TRANSMISSION_MODE_2K:
deb_setf("2k\n");
wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
break;
case TRANSMISSION_MODE_8K:
deb_setf("8k\n");
wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
break;
case TRANSMISSION_MODE_AUTO:
deb_setf("auto\n");
break;
default:
return -EINVAL;
}
deb_setf("guard: ");
switch (ofdm->guard_interval) {
case GUARD_INTERVAL_1_32:
deb_setf("1_32\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
break;
case GUARD_INTERVAL_1_16:
deb_setf("1_16\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
break;
case GUARD_INTERVAL_1_8:
deb_setf("1_8\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
break;
case GUARD_INTERVAL_1_4:
deb_setf("1_4\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
break;
case GUARD_INTERVAL_AUTO:
deb_setf("auto\n");
break;
default:
return -EINVAL;
}
deb_setf("inversion: ");
switch (fep->inversion) {
case INVERSION_OFF:
deb_setf("off\n");
wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
break;
case INVERSION_AUTO:
deb_setf("auto ");
break;
case INVERSION_ON:
deb_setf("on\n");
wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
break;
default:
return -EINVAL;
}
deb_setf("constellation: ");
switch (ofdm->constellation) {
case QPSK:
deb_setf("qpsk\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
break;
case QAM_16:
deb_setf("qam16\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
break;
case QAM_64:
deb_setf("qam64\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
break;
case QAM_AUTO:
break;
default:
return -EINVAL;
}
deb_setf("hierachy: ");
switch (ofdm->hierarchy_information) {
case HIERARCHY_NONE:
deb_setf("none ");
/* fall through */
case HIERARCHY_1:
deb_setf("alpha=1\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
break;
case HIERARCHY_2:
deb_setf("alpha=2\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
break;
case HIERARCHY_4:
deb_setf("alpha=4\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
break;
case HIERARCHY_AUTO:
deb_setf("alpha=auto\n");
break;
default:
return -EINVAL;
}
deb_setf("hierarchy: ");
if (ofdm->hierarchy_information == HIERARCHY_NONE) {
deb_setf("none\n");
wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
fe_cr = ofdm->code_rate_HP;
} else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
deb_setf("on\n");
wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
fe_cr = ofdm->code_rate_LP;
}
deb_setf("fec: ");
switch (fe_cr) {
case FEC_1_2:
deb_setf("1_2\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
break;
case FEC_2_3:
deb_setf("2_3\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
break;
case FEC_3_4:
deb_setf("3_4\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
break;
case FEC_5_6:
deb_setf("5_6\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
break;
case FEC_7_8:
deb_setf("7_8\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
break;
case FEC_NONE:
deb_setf("none ");
break;
case FEC_AUTO:
deb_setf("auto\n");
break;
default:
return -EINVAL;
}
seq = dib3000_seq
[ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
[ofdm->guard_interval == GUARD_INTERVAL_AUTO]
[fep->inversion == INVERSION_AUTO];
deb_setf("seq? %d\n",seq);
wr(DIB3000MB_REG_SEQ,seq);
wr(DIB3000MB_REG_ISI,seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_2K_1_8);
} else {
wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_DEFAULT);
}
wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_2K);
} else {
wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_DEFAULT);
}
wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_OFF);
wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
wr(DIB3000MB_REG_MOBILE_MODE,DIB3000MB_MOBILE_MODE_OFF);
wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_high);
wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_ACTIVATE);
wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AGC+DIB3000MB_RESTART_CTRL);
wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
/* wait for AGC lock */
msleep(70);
wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
/* something has to be auto searched */
if (ofdm->constellation == QAM_AUTO ||
ofdm->hierarchy_information == HIERARCHY_AUTO ||
fe_cr == FEC_AUTO ||
fep->inversion == INVERSION_AUTO) {
int as_count=0;
deb_setf("autosearch enabled.\n");
wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AUTO_SEARCH);
wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
while ((search_state =
dib3000_search_status(
rd(DIB3000MB_REG_AS_IRQ_PENDING),
rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
msleep(1);
deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
if (search_state == 1) {
struct dvb_frontend_parameters feps;
if (dib3000mb_get_frontend(fe, &feps) == 0) {
deb_setf("reading tuning data from frontend succeeded.\n");
return dib3000mb_set_frontend(fe, &feps, 0);
}
}
} else {
wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_CTRL);
wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
}
return 0;
}
static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
{
struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_UP);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE);
wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE_RST);
wr(DIB3000MB_REG_CLOCK,DIB3000MB_CLOCK_DEFAULT);
wr(DIB3000MB_REG_ELECT_OUT_MODE,DIB3000MB_ELECT_OUT_MODE_ON);
wr(DIB3000MB_REG_DDS_FREQ_MSB,DIB3000MB_DDS_FREQ_MSB);
wr(DIB3000MB_REG_DDS_FREQ_LSB,DIB3000MB_DDS_FREQ_LSB);
wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
wr_foreach(dib3000mb_reg_impulse_noise,
dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
wr_foreach(dib3000mb_reg_agc_gain,dib3000mb_default_agc_gain);
wr(DIB3000MB_REG_PHASE_NOISE,DIB3000MB_PHASE_NOISE_DEFAULT);
wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
wr_foreach(dib3000mb_reg_lock_duration,dib3000mb_default_lock_duration);
wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
wr(DIB3000MB_REG_LOCK0_MASK,DIB3000MB_LOCK0_DEFAULT);
wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
wr(DIB3000MB_REG_LOCK2_MASK,DIB3000MB_LOCK2_DEFAULT);
wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
wr(DIB3000MB_REG_UNK_68,DIB3000MB_UNK_68);
wr(DIB3000MB_REG_UNK_69,DIB3000MB_UNK_69);
wr(DIB3000MB_REG_UNK_71,DIB3000MB_UNK_71);
wr(DIB3000MB_REG_UNK_77,DIB3000MB_UNK_77);
wr(DIB3000MB_REG_UNK_78,DIB3000MB_UNK_78);
wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
wr(DIB3000MB_REG_UNK_92,DIB3000MB_UNK_92);
wr(DIB3000MB_REG_UNK_96,DIB3000MB_UNK_96);
wr(DIB3000MB_REG_UNK_97,DIB3000MB_UNK_97);
wr(DIB3000MB_REG_UNK_106,DIB3000MB_UNK_106);
wr(DIB3000MB_REG_UNK_107,DIB3000MB_UNK_107);
wr(DIB3000MB_REG_UNK_108,DIB3000MB_UNK_108);
wr(DIB3000MB_REG_UNK_122,DIB3000MB_UNK_122);
wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
wr(DIB3000MB_REG_BERLEN,DIB3000MB_BERLEN_DEFAULT);
wr_foreach(dib3000mb_reg_filter_coeffs,dib3000mb_filter_coeffs);
wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_ON);
wr(DIB3000MB_REG_MULTI_DEMOD_MSB,DIB3000MB_MULTI_DEMOD_MSB);
wr(DIB3000MB_REG_MULTI_DEMOD_LSB,DIB3000MB_MULTI_DEMOD_LSB);
wr(DIB3000MB_REG_OUTPUT_MODE,DIB3000MB_OUTPUT_MODE_SLAVE);
wr(DIB3000MB_REG_FIFO_142,DIB3000MB_FIFO_142);
wr(DIB3000MB_REG_MPEG2_OUT_MODE,DIB3000MB_MPEG2_OUT_MODE_188);
wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
wr(DIB3000MB_REG_FIFO,DIB3000MB_FIFO_INHIBIT);
wr(DIB3000MB_REG_FIFO_146,DIB3000MB_FIFO_146);
wr(DIB3000MB_REG_FIFO_147,DIB3000MB_FIFO_147);
wr(DIB3000MB_REG_DATA_IN_DIVERSITY,DIB3000MB_DATA_DIVERSITY_IN_OFF);
if (state->config.pll_init) {
wr(DIB3000MB_REG_TUNER,
DIB3000_TUNER_WRITE_ENABLE(state->config.pll_addr));
state->config.pll_init(fe);
wr(DIB3000MB_REG_TUNER,
DIB3000_TUNER_WRITE_DISABLE(state->config.pll_addr));
}
return 0;
}
