static void disp_aal_set_interrupt(int enabled)
{
#ifdef CONFIG_MTK_AAL_SUPPORT
if (enabled) {
if (DISP_REG_GET(DISP_AAL_EN) == 0) {
AAL_DBG("[WARNING] DISP_AAL_EN not enabled!");
}
/* Enable output frame end interrupt */
DISP_CPU_REG_SET(DISP_AAL_INTEN, 0x2);
AAL_DBG("Interrupt enabled");
} else {
if (g_aal_dirty_frame_retrieved) {
DISP_CPU_REG_SET(DISP_AAL_INTEN, 0x0);
AAL_DBG("Interrupt disabled");
} else { /* Dirty histogram was not retrieved */
/* Only if the dirty hist was retrieved, interrupt can be disabled.
Continue interrupt until AALService can get the latest histogram. */
}
}
#else
AAL_ERR("AAL driver is not enabled");
#endif
}
void disp_set_pll(unsigned int freq)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
if (freq == freq_last)
return;
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 182) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_182MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_182MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 364) {
clkmux_sel(MT_MUX_MM, 1, DISP_CLOCK_USER_NAME);
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
}
static int RDMAPollingInterrupt(DISP_MODULE_ENUM module, int bit, int timeout)
{
unsigned int idx = rdma_index(module);
unsigned int cnt = 0;
unsigned int regval = 0;
if( timeout <= 0)
{
while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS) & bit)==0);
cnt = 1;
}
else
{
// time need to update
cnt = timeout*1000/100;
while(cnt > 0)
{
cnt--;
regval = DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS);
if(regval & bit )
{
DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS, ~regval);
break;
}
udelay(100);
}
}
//should clear?
DDPMSG(" RDMA%d polling interrupt ret =%d \n", idx, cnt);
return cnt;
}
void disp_aal_on_end_of_frame(void)
{
unsigned int intsta;
int i;
unsigned long flags;
intsta = DISP_REG_GET(DISP_AAL_INTSTA);
AAL_DBG("disp_aal_on_end_of_frame: intsta: 0x%x", intsta);
if (intsta & 0x2) { /* End of frame */
if (spin_trylock_irqsave(&g_aal_hist_lock, flags)) {
DISP_CPU_REG_SET(DISP_AAL_INTSTA, (intsta & ~0x3));
for (i = 0; i < AAL_HIST_BIN; i++) {
g_aal_hist.maxHist[i] = DISP_REG_GET(DISP_AAL_STATUS_00 + (i << 2));
}
g_aal_hist_available = 1;
/* Allow to disable interrupt */
g_aal_dirty_frame_retrieved = 1;
spin_unlock_irqrestore(&g_aal_hist_lock, flags);
wake_up_interruptible(&g_aal_hist_wq);
} else {
/*
* Histogram was not be retrieved, but it's OK.
* Another interrupt will come until histogram available
* See: disp_aal_set_interrupt()
*/
}
}
}
int OVLReset(DISP_MODULE_ENUM module,void * handle) {
#define OVL_IDLE (0x3)
unsigned int delay_cnt = 0;
int idx = ovl_index(module);
/*always use cpu do reset*/
DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_OVL_RST, 0x1); // soft reset
DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_OVL_RST, 0x0);
while(!(DISP_REG_GET(idx*DISP_INDEX_OFFSET+DISP_REG_OVL_FLOW_CTRL_DBG) & OVL_IDLE))
{
delay_cnt++;
udelay(10);
if(delay_cnt>2000)
{
DDPERR("OVL%dReset() timeout! \n",idx);
break;
}
}
return 0;
}
int ovl_reset(DISP_MODULE_ENUM module, void *handle)
{
#define OVL_IDLE (0x3)
int ret = 0;
unsigned int delay_cnt = 0;
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_CPU_REG_SET(idx_offset+DISP_REG_OVL_RST, 0x1);
DISP_CPU_REG_SET(idx_offset+DISP_REG_OVL_RST, 0x0);
/*only wait if not cmdq*/
if (handle == NULL) {
while (!(DISP_REG_GET(idx_offset+DISP_REG_OVL_FLOW_CTRL_DBG) & OVL_IDLE)) {
delay_cnt++;
udelay(10);
if (delay_cnt > 2000) {
DDPERR("ovl%d_reset timeout!\n", idx);
ret = -1;
break;
}
}
}
return ret;
}
void disp_aal_on_end_of_frame(void)
{
#ifdef CONFIG_MTK_AAL_SUPPORT
unsigned int intsta;
int i;
unsigned long flags;
intsta = DISP_REG_GET(DISP_AAL_INTSTA);
AAL_DBG("disp_aal_on_end_of_frame: intsta: 0x%x", intsta);
if (intsta & 0x2) { /* End of frame */
if (spin_trylock_irqsave(&g_aal_hist_lock, flags)) {
DISP_CPU_REG_SET(DISP_AAL_INTSTA, (intsta & ~0x3));
for (i = 0; i < AAL_HIST_BIN; i++) {
g_aal_hist.maxHist[i] = DISP_REG_GET(DISP_AAL_STATUS_00 + (i << 2));
}
g_aal_hist_available = 1;
/* Allow to disable interrupt */
g_aal_dirty_frame_retrieved = 1;
spin_unlock_irqrestore(&g_aal_hist_lock, flags);
if (!g_aal_is_init_regs_valid) {
/*
* AAL service is not running, not need per-frame wakeup.
* We stop interrupt until next frame dirty.
*/
disp_aal_set_interrupt(0);
}
wake_up_interruptible(&g_aal_hist_wq);
} else {
/*
* Histogram was not be retrieved, but it's OK.
* Another interrupt will come until histogram available
* See: disp_aal_set_interrupt()
*/
}
}
#else
/*
* We will not wake up AAL unless signals
*/
#endif
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
static disp_session_config config;
if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16);
if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U)
{
unsigned int regVal = DISP_REG_GET(addr);
DDPMSG("regr: 0x%lx = 0x%08X\n", addr, regVal);
sprintf(buf, "regr: 0x%lx = 0x%08X\n", addr, regVal);
} else {
sprintf(buf, "regr, invalid address 0x%lx\n", addr);
goto Error;
}
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16);
unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U)
{
unsigned int regVal;
DISP_CPU_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DDPMSG("regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal);
sprintf(buf, "regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal);
} else {
sprintf(buf, "regw, invalid address 0x%lx \n", addr);
goto Error;
}
}
else if (0 == strncmp(opt, "dbg_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
dbg_log_level = 1;
else
dbg_log_level = 0;
sprintf(buf, "dbg_log: %d\n", dbg_log_level);
}
else if (0 == strncmp(opt, "irq_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_log_level = 1;
else
irq_log_level = 0;
sprintf(buf, "irq_log: %d\n", irq_log_level);
}
else if (0 == strncmp(opt, "met_on:", 7))
{
char *p = (char *)opt + 7;
int met_on = (int) simple_strtoul(p, &p, 10);
int rdma0_mode = (int) simple_strtoul(p + 1, &p, 10);
int rdma1_mode = (int) simple_strtoul(p + 1, &p, 10);
// ddp_init_met_tag(met_on,rdma0_mode,rdma1_mode);
DDPMSG("process_dbg_opt, met_on=%d,rdma0_mode %d, rdma1 %d \n", met_on,rdma0_mode,rdma1_mode);
sprintf(buf, "met_on:%d,rdma0_mode:%d,rdma1_mode:%d\n", met_on,rdma0_mode,rdma1_mode);
}
else if (0 == strncmp(opt, "backlight:", 10))
{
char *p = (char *)opt + 10;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
if (level)
{
disp_bls_set_backlight(level);
sprintf(buf, "backlight: %d\n", level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "pwm0:", 5) || 0 == strncmp(opt, "pwm1:", 5))
{
char *p = (char *)opt + 5;
unsigned int level = (unsigned int)simple_strtoul(p, &p, 10);
if (level)
{
disp_pwm_id_t pwm_id = DISP_PWM0;
if (opt[3] == '1')
pwm_id = DISP_PWM1;
disp_pwm_set_backlight(pwm_id, level);
sprintf(buf, "PWM 0x%x : %d\n", pwm_id, level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "aal_dbg:", 8))
{
aal_dbg_en = (int)simple_strtoul(opt + 8, NULL, 10);
sprintf(buf, "aal_dbg_en = 0x%x\n", aal_dbg_en);
}
else if (0 == strncmp(opt, "dump_reg:", 9))
{
char *p = (char *)opt + 9;
unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
DDPMSG("process_dbg_opt, module=%d \n", module);
if (module<DISP_MODULE_NUM)
{
ddp_dump_reg(module);
sprintf(buf, "dump_reg: %d\n", module);
} else {
DDPMSG("process_dbg_opt2, module=%d \n", module);
goto Error;
}
}
else if (0 == strncmp(opt, "dump_path:", 10))
{
char *p = (char *)opt + 10;
unsigned int mutex_idx = (unsigned int) simple_strtoul(p, &p, 10);
DDPMSG("process_dbg_opt, path mutex=%d \n", mutex_idx);
dpmgr_debug_path_status(mutex_idx);
sprintf(buf, "dump_path: %d\n", mutex_idx);
}
else if (0 == strncmp(opt, "debug:", 6))
{
char *p = (char *)opt + 6;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if(enable==1)
{
DDPMSG("[DDP] debug=1, trigger AEE\n");
//aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
}
else if(enable==2)
{
ddp_mem_test();
}
else if(enable==3)
{
ddp_lcd_test();
}
else if(enable==4)
{
//DDPAEE("test 4");
}
else if(enable==5)
{
extern unsigned int gDDPError;
if(gDDPError==0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
}
else if(enable==6)
{
unsigned int i = 0;
int * modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
printk("dump path status:");
for(i=0;i<module_num;i++)
{
printk("%s-", ddp_get_module_name(modules[i]));
}
printk("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for( i=0; i< module_num;i++)
{
ddp_dump_analysis(modules[i]);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
for( i=0; i< module_num;i++)
{
ddp_dump_reg(modules[i]);
}
}
else if(enable==7)
{
if(dbg_log_level<3)
dbg_log_level++;
else
dbg_log_level=0;
printk("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
}
#if 0
else if(enable==8)
{
DDPDUMP("clock_mm setting:%u \n",
DISP_REG_GET(DISP_REG_CONFIG_C11));
if(DISP_REG_GET(DISP_REG_CONFIG_C11)&0xff000000!=0xff000000)
{
DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x", DISP_REG_GET(DISP_REG_CONFIG_C11));
}
}
#endif
else if(enable==9)
{
gOVLBackground = 0xFF0000FF;
printk("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
}
else if(enable==10)
{
gOVLBackground = 0xFF000000;
printk("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
}
else if(enable==11)
{
unsigned int i=0;
for(i=0;i<DISP_REG_NUM;i++)
{
DDPDUMP("i=%d, module=%s, reg_va=0x%lx\n", i, ddp_get_reg_module_name(i), dispsys_reg[i]);
}
}
else if(enable==12)
{
if(gUltraEnable==0)
gUltraEnable = 1;
else
gUltraEnable = 0;
printk("DDP: gUltraEnable=%d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
}
}
else if (0 == strncmp(opt, "mmp", 3))
{
init_ddp_mmp_events();
}
else
{
dbg_buf[0]='\0';
goto Error;
}
return;
Error:
DDPERR("parse command error!\n%s\n\n%s", opt, STR_HELP);
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
if (0 == strncmp(opt, "regr:", 5)) {
unsigned long addr;
int ret;
ret = sscanf(opt, "regr: 0x%lx\n", &addr);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (is_reg_addr_valid(1, addr) == 1) {
unsigned int regVal = DISP_REG_GET(addr);
DDPMSG(" regr : 0x%lx = 0x%08x\n ", addr, regVal);
sprintf(buf, " regr : 0x%lx = 0x%08x\n ", addr, regVal);
} else {
sprintf(buf, " regr, invalid address 0x%lx\n ", addr);
goto Error;
}
} else if (0 == strncmp(opt, "regw:", 5)) {
unsigned long addr;
unsigned int val;
unsigned int ret;
ret = sscanf(opt, "regw: 0x%lx,0x%08x\n", &addr, &val);
if (ret != 2) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (is_reg_addr_valid(1, addr) == 1) {
unsigned int regVal;
DISP_CPU_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DDPMSG(" regw : 0x%lx, 0x%08x = 0x%08x\n ", addr, val, regVal);
sprintf(buf, " regw : 0x%lx, 0x%08x = 0x%08x\n ", addr, val, regVal);
} else {
sprintf(buf, " regw, invalid address 0x%lx\n ", addr);
goto Error;
}
} else if (0 == strncmp(opt, "rdma_ultra:", 11)) {
int ret;
ret = sscanf(opt, "rdma_ultra: 0x%x\n", &gRDMAUltraSetting);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
DISP_CPU_REG_SET(DISP_REG_RDMA_MEM_GMC_SETTING_0, gRDMAUltraSetting);
sprintf(buf, " rdma_ultra, gRDMAUltraSetting = 0x%x, reg = 0x%x\n ", gRDMAUltraSetting,
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0));
} else if (0 == strncmp(opt, "rdma_fifo:", 10)) {
int ret;
ret = sscanf(opt, "rdma_fifo: 0x%x\n", &gRDMAFIFOLen);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
DISP_CPU_REG_SET_FIELD(FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD,
DISP_REG_RDMA_FIFO_CON, gRDMAFIFOLen);
sprintf(buf, " rdma_fifo, gRDMAFIFOLen = 0x%x, reg = 0x%x\n ", gRDMAFIFOLen,
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
} else if (0 == strncmp(opt, "g_regr:", 7)) {
unsigned int reg_va_before;
unsigned long reg_va;
unsigned long reg_pa;
int ret;
ret = sscanf(opt, "g_regr: 0x%lx\n", ®_pa);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (reg_pa < 0x10000000 || reg_pa > 0x18000000) {
sprintf(buf, " g_regr, invalid pa = 0x%lx\n ", reg_pa);
} else {
reg_va = (unsigned long)ioremap_nocache(reg_pa, sizeof(unsigned long));
reg_va_before = DISP_REG_GET(reg_va);
pr_debug(" g_regr, pa = 0x%lx, va = 0x%lx, reg_val = 0x%x\n ",
reg_pa, reg_va, reg_va_before);
sprintf(buf, " g_regr, pa = 0x%lx, va = 0x%lx, reg_val = 0x%x\n ",
reg_pa, reg_va, reg_va_before);
iounmap((void *)reg_va);
}
} else if (0 == strncmp(opt, "g_regw:", 7)) {
unsigned int reg_va_before;
unsigned int reg_va_after;
unsigned int val;
unsigned long reg_va;
unsigned long reg_pa;
int ret;
ret = sscanf(opt, "g_regw: 0x%lx\n", ®_pa);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (reg_pa < 0x10000000 || reg_pa > 0x18000000) {
sprintf(buf, " g_regw, invalid pa = 0x%lx\n ", reg_pa);
} else {
ret = sscanf(opt, "g_regw,val: 0x%x\n", &val);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
reg_va = (unsigned long)ioremap_nocache(reg_pa, sizeof(unsigned long));
reg_va_before = DISP_REG_GET(reg_va);
DISP_CPU_REG_SET(reg_va, val);
reg_va_after = DISP_REG_GET(reg_va);
pr_debug
("g_regw, pa = 0x%lx, va = 0x%lx, value = 0x%x, reg_val_before = 0x%x, reg_val_after = 0x%x\n ",
reg_pa, reg_va, val, reg_va_before, reg_va_after);
sprintf(buf,
" g_regw, pa = 0x%lx, va = 0x%lx, value = 0x%x, reg_val_before = 0x%x, reg_val_after = 0x%x\n ",
reg_pa, reg_va, val, reg_va_before, reg_va_after);
iounmap((void *)reg_va);
}
} else if (0 == strncmp(opt, "dbg_log:", 8)) {
unsigned int enable;
int ret;
ret = sscanf(opt, "dbg_log: %d\n", &enable);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (enable)
dbg_log_level = 1;
else
dbg_log_level = 0;
sprintf(buf, " dbg_log : %d\n ", dbg_log_level);
} else if (0 == strncmp(opt, "irq_log:", 8)) {
unsigned int enable;
int ret;
ret = sscanf(opt, "irq_log: %d\n", &enable);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (enable)
irq_log_level = 1;
else
irq_log_level = 0;
sprintf(buf, " irq_log : %d\n ", irq_log_level);
} else if (0 == strncmp(opt, "met_on:", 7)) {
int met_on;
int rdma0_mode;
int rdma1_mode;
int ret;
ret = sscanf(opt, "met_on : %d,%d,%d\n",
&met_on, &rdma0_mode, &rdma1_mode);
if (ret != 3) {
pr_err("error to parse cmd %s\n", opt);
return;
}
ddp_init_met_tag(met_on, rdma0_mode, rdma1_mode);
DDPMSG(" process_dbg_opt, met_on = %d, rdma0_mode %d, rdma1 %d\n ", met_on, rdma0_mode,
rdma1_mode);
sprintf(buf, " met_on : %d, rdma0_mode : %d, rdma1_mode : %d\n ", met_on, rdma0_mode,
rdma1_mode);
} else if (0 == strncmp(opt, "backlight:", 10)) {
unsigned int level;
int ret;
ret = sscanf(opt, "backlight: %d\n", &level);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (level) {
disp_bls_set_backlight(level);
sprintf(buf, " backlight : %d\n ", level);
} else {
goto Error;
}
} else if (0 == strncmp(opt, "pwm0:", 5) || 0 == strncmp(opt, "pwm1:", 5)) {
unsigned int level;
int ret;
ret = sscanf(opt, "pwm: %d\n", &level);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
if (level) {
disp_pwm_id_t pwm_id = DISP_PWM0;
if (opt[3] == '1')
pwm_id = DISP_PWM1;
disp_pwm_set_backlight(pwm_id, level);
sprintf(buf, " PWM 0x%x : %d\n ", pwm_id, level);
} else {
goto Error;
}
} else if (0 == strncmp(opt, "aal_dbg:", 8)) {
int ret;
ret = sscanf(opt, "aal_dbg: %d\n", &aal_dbg_en);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
sprintf(buf, " aal_dbg_en = 0x%x\n ", aal_dbg_en);
} else if (0 == strncmp(opt, "dump_reg:", 9)) {
unsigned int module;
int ret;
ret = sscanf(opt, "dump_reg: %d\n", &module);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
DDPMSG(" process_dbg_opt, module = %d\n ", module);
if (module < DISP_MODULE_NUM) {
ddp_dump_reg(module);
sprintf(buf, " dump_reg : %d\n ", module);
} else {
DDPMSG(" process_dbg_opt2, module = %d\n ", module);
goto Error;
}
} else if (0 == strncmp(opt, "dump_path:", 10)) {
unsigned int mutex_idx;
int ret;
ret = sscanf(opt, "dump_path: %d\n", &mutex_idx);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
DDPMSG(" process_dbg_opt, path mutex = %d\n ", mutex_idx);
dpmgr_debug_path_status(mutex_idx);
sprintf(buf, " dump_path : %d\n ", mutex_idx);
} else if (0 == strncmp(opt, "debug:", 6)) {
unsigned int enable;
int ret;
ret = sscanf(opt, "debug: %d\n", &enable);
if (ret != 1) {
pr_err("error to parse cmd %s\n", opt);
return;
}
disp_debug_api(enable, buf);
} else if (0 == strncmp(opt, "mmp", 3)) {
init_ddp_mmp_events();
} else {
dbg_buf[0] = '\0';
goto Error;
}
return;
Error:
DDPERR(" parse command error !\n%s\n\n%s", opt, STR_HELP);
}
static void disp_debug_api(unsigned int enable, char *buf)
{
if (enable == 1) {
DDPMSG("[DDP] debug=1, trigger AEE\n");
/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
} else if (enable == 2) {
ddp_mem_test();
} else if (enable == 3) {
ddp_lcd_test();
} else if (enable == 4) {
DDPAEE("test enable=%d\n", enable);
sprintf(buf, "test enable=%d\n", enable);
} else if (enable == 5) {
if (gDDPError == 0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
} else if (enable == 6) {
/*ddp_dump_analysis(DISP_MODULE_DSI0);*/
ddp_dump_reg(DISP_MODULE_DSI0);
} else if (enable == 7) {
if (dbg_log_level < 3)
dbg_log_level++;
else
dbg_log_level = 0;
pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
} else if (enable == 8) {
DDPDUMP("clock_mm setting:%u\n",
DISP_REG_GET(DISP_REG_CONFIG_C11));
if (DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000 !=
0xff000000) {
DDPDUMP
("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
DISP_REG_GET(DISP_REG_CONFIG_C11));
}
} else if (enable == 9) {
gOVLBackground = 0xFF0000FF;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 10) {
gOVLBackground = 0xFF000000;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 11) {
dispsys_irq[DISP_REG_NUM];
ddp_irq_num[DISP_REG_NUM];
unsigned int i = 0;
char *buf_temp = buf;
for (i = 0; i < DISP_REG_NUM; i++) {
DDPDUMP
("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i],
ddp_irq_num[i]);
sprintf(buf_temp,
"i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i],
ddp_irq_num[i]);
buf_temp += strlen(buf_temp);
}
} else if (enable == 12) {
if (gUltraEnable == 0)
gUltraEnable = 1;
else
gUltraEnable = 0;
pr_debug("DDP : gUltraEnable = %d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
} else if (enable == 13) {
/*int ovl_status = ovl_get_status();
config.type = DISP_SESSION_MEMORY;
config.device_id = 0;
disp_create_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
} else if (enable == 14) {
/*int ovl_status = ovl_get_status();
disp_destroy_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
} else if (enable == 15) {
/* extern smi_dumpDebugMsg(void); */
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_RDMA0);
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_OVL1);
/* dump ultra/preultra related regs */
DDPMSG("wdma_con1(2c) = 0x%x, wdma_con2(0x38) = 0x%x, rdma_gmc0(30) = 0x%x",
DISP_REG_GET(DISP_REG_WDMA_BUF_CON1), DISP_REG_GET(DISP_REG_WDMA_BUF_CON2),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0));
DDPMSG(" rdma_gmc1(38) = 0x%x, fifo_con(40) = 0x%x\n ",
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
DDPMSG(" ovl0_gmc : 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc : 0x%x, 0x%x, 0x%x, 0x%x\n ",
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET));
/* dump smi regs */
/* smi_dumpDebugMsg(); */
} else if (enable == 16) {
if (gDumpMemoutCmdq == 0)
gDumpMemoutCmdq = 1;
else
gDumpMemoutCmdq = 0;
pr_debug(" DDP : gDumpMemoutCmdq = %d\n ", gDumpMemoutCmdq);
sprintf(buf, " gDumpMemoutCmdq : %d\n ", gDumpMemoutCmdq);
} else if (enable == 21) {
if (gEnableSODIControl == 0)
gEnableSODIControl = 1;
else
gEnableSODIControl = 0;
pr_debug(" DDP : gEnableSODIControl = %d\n ", gEnableSODIControl);
sprintf(buf, " gEnableSODIControl : %d\n ", gEnableSODIControl);
} else if (enable == 22) {
if (gPrefetchControl == 0)
gPrefetchControl = 1;
else
gPrefetchControl = 0;
pr_debug(" DDP : gPrefetchControl = %d\n ", gPrefetchControl);
sprintf(buf, " gPrefetchControl : %d\n ", gPrefetchControl);
} else if (enable == 23) {
if (disp_low_power_enlarge_blanking == 0)
disp_low_power_enlarge_blanking = 1;
else
disp_low_power_enlarge_blanking = 0;
pr_debug(" DDP : disp_low_power_enlarge_blanking = %d\n ",
disp_low_power_enlarge_blanking);
sprintf(buf, " disp_low_power_enlarge_blanking : %d\n ",
disp_low_power_enlarge_blanking);
} else if (enable == 24) {
if (disp_low_power_disable_ddp_clock == 0)
disp_low_power_disable_ddp_clock = 1;
else
disp_low_power_disable_ddp_clock = 0;
pr_debug(" DDP : disp_low_power_disable_ddp_clock = %d\n ",
disp_low_power_disable_ddp_clock);
sprintf(buf, " disp_low_power_disable_ddp_clock : %d\n ",
disp_low_power_disable_ddp_clock);
} else if (enable == 25) {
if (disp_low_power_disable_fence_thread == 0)
disp_low_power_disable_fence_thread = 1;
else
disp_low_power_disable_fence_thread = 0;
pr_debug(" DDP : disp_low_power_disable_fence_thread = %d\n ",
disp_low_power_disable_fence_thread);
sprintf(buf, " disp_low_power_disable_fence_thread : %d\n ",
disp_low_power_disable_fence_thread);
} else if (enable == 26) {
if (disp_low_power_remove_ovl == 0)
disp_low_power_remove_ovl = 1;
else
disp_low_power_remove_ovl = 0;
pr_debug(" DDP : disp_low_power_remove_ovl = %d\n ", disp_low_power_remove_ovl);
sprintf(buf, " disp_low_power_remove_ovl : %d\n ", disp_low_power_remove_ovl);
} else if (enable == 27) {
if (gSkipIdleDetect == 0)
gSkipIdleDetect = 1;
else
gSkipIdleDetect = 0;
pr_debug(" DDP : gSkipIdleDetect = %d\n ", gSkipIdleDetect);
sprintf(buf, " gSkipIdleDetect : %d\n ", gSkipIdleDetect);
} else if (enable == 28) {
if (gDumpClockStatus == 0)
gDumpClockStatus = 1;
else
gDumpClockStatus = 0;
pr_debug(" DDP : gDumpClockStatus = %d\n ", gDumpClockStatus);
sprintf(buf, " gDumpClockStatus : %d\n ", gDumpClockStatus);
} else if (enable == 29) {
if (gEnableUartLog == 0)
gEnableUartLog = 1;
else
gEnableUartLog = 0;
pr_debug(" DDP : gEnableUartLog = %d\n ", gEnableUartLog);
sprintf(buf, " gEnableUartLog : %d\n ", gEnableUartLog);
} else if (enable == 30) {
if (gEnableMutexRisingEdge == 0) {
gEnableMutexRisingEdge = 1;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
1);
} else {
gEnableMutexRisingEdge = 0;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
0);
}
pr_debug(" DDP : gEnableMutexRisingEdge = %d\n ", gEnableMutexRisingEdge);
sprintf(buf, " gEnableMutexRisingEdge : %d\n ", gEnableMutexRisingEdge);
} else if (enable == 31) {
if (gEnableReduceRegWrite == 0)
gEnableReduceRegWrite = 1;
else
gEnableReduceRegWrite = 0;
pr_debug(" DDP : gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite);
sprintf(buf, " gEnableReduceRegWrite : %d\n ", gEnableReduceRegWrite);
} else if (enable == 32) {
/* DDPAEE(" DDP : (32) gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite); */
} else if (enable == 33) {
if (gDumpConfigCMD == 0)
gDumpConfigCMD = 1;
else
gDumpConfigCMD = 0;
pr_debug(" DDP : gDumpConfigCMD = %d\n ", gDumpConfigCMD);
sprintf(buf, " gDumpConfigCMD : %d\n ", gDumpConfigCMD);
} else if (enable == 34) {
if (gESDEnableSODI == 0)
gESDEnableSODI = 1;
else
gESDEnableSODI = 0;
pr_debug(" DDP : gESDEnableSODI = %d\n ", gESDEnableSODI);
sprintf(buf, " gESDEnableSODI : %d\n ", gESDEnableSODI);
} else if (enable == 35) {
if (gEnableOVLStatusCheck == 0)
gEnableOVLStatusCheck = 1;
else
gEnableOVLStatusCheck = 0;
pr_debug(" DDP : gEnableOVLStatusCheck = %d\n ", gEnableOVLStatusCheck);
sprintf(buf, " gEnableOVLStatusCheck : %d\n ", gEnableOVLStatusCheck);
} else if (enable == 36) {
if (gResetRDMAEnable == 0)
gResetRDMAEnable = 1;
else
gResetRDMAEnable = 0;
pr_debug(" DDP : gResetRDMAEnable = %d\n ", gResetRDMAEnable);
sprintf(buf, " gResetRDMAEnable : %d\n ", gResetRDMAEnable);
} else if (enable == 37) {
unsigned int reg_value = 0;
if (gEnableIRQ == 0) {
gEnableIRQ = 1;
/* OVL0/OVL1 */
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);
/* Mutex0 */
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
/* RDMA0 */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x3E);
} else {
gEnableIRQ = 0;
/* OVL0/OVL1 */
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);
/* Mutex0 */
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value & (~(1 << 0)) & (~(1 << DISP_MUTEX_TOTAL)));
/* RDMA0 */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x18);
}
pr_debug(" DDP : gEnableIRQ = %d\n ", gEnableIRQ);
sprintf(buf, " gEnableIRQ : %d\n ", gEnableIRQ);
} else if (enable == 38) {
if (gDisableSODIForTriggerLoop == 0)
gDisableSODIForTriggerLoop = 1;
else
gDisableSODIForTriggerLoop = 0;
pr_debug(" DDP : gDisableSODIForTriggerLoop = %d\n ", gDisableSODIForTriggerLoop);
sprintf(buf, " gDisableSODIForTriggerLoop : %d\n ", gDisableSODIForTriggerLoop);
} else if (enable == 39) {
cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
sprintf(buf, " enable = %d\n ", enable);
} else if (enable == 41) {
if (gResetOVLInAALTrigger == 0)
gResetOVLInAALTrigger = 1;
else
gResetOVLInAALTrigger = 0;
pr_debug(" DDP : gResetOVLInAALTrigger = %d\n ", gResetOVLInAALTrigger);
sprintf(buf, " gResetOVLInAALTrigger : %d\n ", gResetOVLInAALTrigger);
} else if (enable == 42) {
if (gDisableOVLTF == 0)
gDisableOVLTF = 1;
else
gDisableOVLTF = 0;
pr_debug(" DDP : gDisableOVLTF = %d\n ", gDisableOVLTF);
sprintf(buf, " gDisableOVLTF : %d\n ", gDisableOVLTF);
} else if (enable == 43) {
if (gDumpESDCMD == 0)
gDumpESDCMD = 1;
else
gDumpESDCMD = 0;
pr_debug(" DDP : gDumpESDCMD = %d\n ", gDumpESDCMD);
sprintf(buf, " gDumpESDCMD : %d\n ", gDumpESDCMD);
} else if (enable == 44) {
disp_dump_emi_status();
disp_dump_emi_status();
sprintf(buf, " dump emi status !\n ");
} else if (enable == 45) {
if (gEnableCMDQProfile == 0)
gEnableCMDQProfile = 1;
else
gEnableCMDQProfile = 0;
pr_debug(" DDP : gEnableCMDQProfile = %d\n ", gEnableCMDQProfile);
sprintf(buf, " gEnableCMDQProfile : %d\n ", gEnableCMDQProfile);
} else if (enable == 46) {
disp_set_pll(156);
pr_debug(" DDP : disp_set_pll = 156.\n ");
sprintf(buf, " disp_set_pll = 156.\n ");
} else if (enable == 47) {
disp_set_pll(182);
pr_debug(" DDP : disp_set_pll = 182.\n ");
sprintf(buf, " disp_set_pll = 182.\n ");
} else if (enable == 48) {
disp_set_pll(364);
pr_debug(" DDP : disp_set_pll = 364\n ");
sprintf(buf, " disp_set_pll = 364.\n ");
} else if (enable == 49) {
if (gChangeRDMAThreshold == 0)
gChangeRDMAThreshold = 1;
else
gChangeRDMAThreshold = 0;
pr_debug(" DDP : gChangeRDMAThreshold = %d\n ", gChangeRDMAThreshold);
sprintf(buf, " gChangeRDMAThreshold : %d\n ", gChangeRDMAThreshold);
} else if (enable == 50) {
if (gChangeMMClock == 0)
gChangeMMClock = 1;
else
gChangeMMClock = 0;
pr_debug(" DDP : gChangeMMClock = %d\n ", gChangeMMClock);
sprintf(buf, " gChangeMMClock : %d\n ", gChangeMMClock);
} else if (enable == 51) {
if (gEnableUnderflowAEE == 0)
gEnableUnderflowAEE = 1;
else
gEnableUnderflowAEE = 0;
pr_debug(" DDP : gEnableUnderflowAEE = %d\n ", gEnableUnderflowAEE);
sprintf(buf, " gEnableUnderflowAEE : %d\n ", gEnableUnderflowAEE);
} else if (enable == 52) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(156, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 53) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(182, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 54) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(364, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 55) {
if (gIssueRequestThreshold == 0)
gIssueRequestThreshold = 1;
else
gIssueRequestThreshold = 0;
pr_debug(" DDP : gIssueRequestThreshold = %d\n ", gIssueRequestThreshold);
sprintf(buf, " gIssueRequestThreshold : %d\n ", gIssueRequestThreshold);
} else if (enable == 56) {
if (gDisableIRQWhenIdle == 0)
gDisableIRQWhenIdle = 1;
else
gDisableIRQWhenIdle = 0;
pr_debug(" DDP : gDisableIRQWhenIdle = %d\n ", gDisableIRQWhenIdle);
sprintf(buf, " gDisableIRQWhenIdle : %d\n ", gDisableIRQWhenIdle);
} else if (enable == 57) {
if (gEnableSODIWhenIdle == 0)
gEnableSODIWhenIdle = 1;
else
gEnableSODIWhenIdle = 0;
pr_debug(" DDP : gEnableSODIWhenIdle = %d\n ", gEnableSODIWhenIdle);
sprintf(buf, " gEnableSODIWhenIdle : %d\n ", gEnableSODIWhenIdle);
} else if (enable == 58) {
#ifdef DISP_ENABLE_LAYER_FRAME
if (gAddFrame == 0)
gAddFrame = 1;
else
gAddFrame = 0;
pr_debug(" DDP : gAddFrame = %d\n ", gAddFrame);
sprintf(buf, " gAddFrame : %d\n ", gAddFrame);
#else
pr_debug(" Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
sprintf(buf, " Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
#endif
} else if (enable == 40) {
sprintf(buf, " version : %d, %s\n ", 12, __TIME__);
} else if (enable==59) {
extern void ddp_reset_test(void);
ddp_reset_test();
sprintf(buf, " dp_reset_test called. \n ");
} else if (enable == 60) {
unsigned int i = 0;
int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
pr_debug("dump path status:");
for (i = 0; i < module_num; i++)
pr_debug("%s-", ddp_get_module_name(modules[i]));
pr_debug("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for (i = 0; i < module_num; i++)
ddp_dump_analysis(modules[i]);
if (primary_display_is_decouple_mode()) {
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_WDMA0);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
if (primary_display_is_decouple_mode()) {
ddp_dump_reg(DISP_MODULE_OVL0);
ddp_dump_reg(DISP_MODULE_OVL1);
ddp_dump_reg(DISP_MODULE_WDMA0);
}
for (i = 0; i < module_num; i++)
ddp_dump_reg(modules[i]);
}
}
unsigned int disp_set_pll_by_cmdq(unsigned int freq, void *cmdq_handle)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
unsigned int i = 0;
if (freq == freq_last)
/* return; */
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
cmdqRecWaitNoClear(cmdq_handle, CMDQ_EVENT_MUTEX0_STREAM_EOF);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
pll_cnt++;
/* set mux to 3 by CMDQ */
DISP_REG_SET_PA(cmdq_handle, 0x10000048, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000044, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000004, 8);
} else if (freq == 182) {
/*NOT USE*/
} else if (freq == 364) {
/* set mux to 1 by CMDQ */
DISP_REG_SET_PA(cmdq_handle, 0x10000048, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000044, 0x1000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000004, 8);
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
/* cmdqRecDumpCommand(cmdq_handle); */
cmdqRecFlush(cmdq_handle);
if (freq == 364) {
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
return 0; /* cmdqRecEstimateEommandExecTime(cmdq_handle); */
}
static void process_dbg_opt(const char *opt)
{
if (0 == strncmp(opt, "stop_trigger_loop", 17))
{
_cmdq_stop_trigger_loop();
return;
}
else if (0 == strncmp(opt, "start_trigger_loop", 18))
{
_cmdq_start_trigger_loop();
return;
}
else if (0 == strncmp(opt, "cmdqregw:", 9))
{
char *p = (char *)opt + 9;
unsigned int addr = simple_strtoul(p, &p, 16);
unsigned int val = simple_strtoul(p + 1, &p, 16);
if (addr) {
primary_display_cmdq_set_reg(addr, val);
} else {
return;
}
}
else if (0 == strncmp(opt, "idle_switch_DC", 14))
{
if (0 == strncmp(opt + 14, "on", 2))
{
enable_screen_idle_switch_decouple();
printk("enable screen_idle_switch_decouple\n");
}
else if (0 == strncmp(opt + 14, "off", 3))
{
disable_screen_idle_switch_decouple();
printk("disable screen_idle_switch_decouple\n");
}
}
else if (0 == strncmp(opt, "shortpath", 9))
{
char *p = (char *)opt + 10;
int s = simple_strtoul(p, &p, 10);
DISPMSG("will %s use shorter decouple path\n", s?"":"not");
disp_helper_set_option(DISP_HELPER_OPTION_TWO_PIPE_INTERFACE_PATH, s);
}
else if (0 == strncmp(opt, "helper", 6))
{
char *p = (char *)opt + 7;
int option = simple_strtoul(p, &p, 10);
int value = simple_strtoul(p + 1, &p, 10);
DISPMSG("will set option %d to %d\n", option, value);
disp_helper_set_option(option, value);
}
else if (0 == strncmp(opt, "dc565", 5))
{
char *p = (char *)opt + 6;
int s = simple_strtoul(p, &p, 10);
DISPMSG("will %s use RGB565 decouple path\n", s?"":"not");
disp_helper_set_option(DISP_HELPER_OPTION_DECOUPLE_MODE_USE_RGB565, s);
}
else if (0 == strncmp(opt, "switch_mode:", 12))
{
int session_id = MAKE_DISP_SESSION(DISP_SESSION_PRIMARY,0);
char *p = (char *)opt + 12;
unsigned long sess_mode = simple_strtoul(p, &p, 10);
primary_display_switch_mode(sess_mode, session_id, 1);
}
else if (0 == strncmp(opt, "dsipattern", 10))
{
char *p = (char *)opt + 11;
unsigned int pattern = (unsigned int) simple_strtoul(p, &p, 16);
if (pattern)
{
DSI_BIST_Pattern_Test(DISP_MODULE_DSI0,NULL,true,pattern);
DISPMSG("enable dsi pattern: 0x%08x\n", pattern);
}
else
{
primary_display_manual_lock();
DSI_BIST_Pattern_Test(DISP_MODULE_DSI0,NULL,false,0);
primary_display_manual_unlock();
return;
}
}
else if (0 == strncmp(opt, "rdma_color:", 11))
{
printk("zeng: rdma_color\n");
if (0 == strncmp(opt + 11, "on", 2))
{
printk("zeng:rdma_color on\n");
char *p = (char *)opt + 14;
unsigned int red = simple_strtoul(p, &p, 10);
unsigned int green = simple_strtoul(p + 1, &p, 10);
unsigned int blue = simple_strtoul(p + 1, &p, 10);
rdma_color_matrix matrix = {0};
rdma_color_pre pre = {0};
rdma_color_post post = {255, 0, 0};
post.ADD0 = red;
post.ADD1 = green;
post.ADD2 = blue;
rdma_set_color_matrix(DISP_MODULE_RDMA0, &matrix, &pre, &post);
rdma_enable_color_transform(DISP_MODULE_RDMA0);
}
else if (0 == strncmp(opt + 11, "off", 3))
{
printk("zeng:rdma_color off\n");
rdma_disable_color_transform(DISP_MODULE_RDMA0);
}
}
else if (0 == strncmp(opt, "diagnose", 8))
{
primary_display_diagnose();
return;
}
else if (0 == strncmp(opt, "_efuse_test", 11))
{
primary_display_check_test();
}
else if (0 == strncmp(opt, "dprec_reset", 11))
{
dprec_logger_reset_all();
return;
}
else if (0 == strncmp(opt, "suspend", 4))
{
primary_display_suspend();
return;
}
else if (0 == strncmp(opt, "ata",3))
{
mtkfb_fm_auto_test();
return;
}
else if (0 == strncmp(opt, "resume", 4))
{
primary_display_resume();
}
else if (0 == strncmp(opt, "dalprintf", 9))
{
DAL_Printf("display aee layer test\n");
}
else if (0 == strncmp(opt, "dalclean", 8))
{
DAL_Clean();
}
else if(0 == strncmp(opt, "lfr_setting:",12))
{
char *p = (char *)opt + 12;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 12);
unsigned int mode = (unsigned int)simple_strtoul(p+1, &p, 12);
LCM_PARAMS lcm_param;
//unsigned int mode=3;
unsigned int type=0;
unsigned int skip_num = 1;
printk("--------------enable/disable lfr--------------\n");
if (enable)
{
printk("lfr enable %d mode =%d\n",enable,mode);
enable=1;
DSI_Set_LFR(DISP_MODULE_DSI0, NULL,mode,type,enable,skip_num);
}else{
printk("lfr disable %d mode=%d\n",enable,mode);
enable=0;
DSI_Set_LFR(DISP_MODULE_DSI0, NULL,mode,type,enable,skip_num);
}
}
else if(0 == strncmp(opt, "vsync_switch:",13))
{
char *p = (char *)opt + 13;
unsigned int method = 0;
method =(unsigned int) simple_strtoul(p, &p, 13);
primary_display_vsync_switch(method);
}
else if (0 == strncmp(opt, "DP", 2))
{
char *p = (char *)opt + 3;
unsigned int pattern = (unsigned int) simple_strtoul(p, &p, 16);
g_display_debug_pattern_index = pattern;
return;
}
else if(0==strncmp(opt,"dsi0_clk:",9))
{
char*p=(char*)opt+9;
UINT32 clk=simple_strtoul(p, &p, 10);
// DSI_ChangeClk(DISP_MODULE_DSI0,clk);
}
else if (0 == strncmp(opt, "diagnose", 8))
{
primary_display_diagnose();
return;
}
else if (0 == strncmp(opt, "switch:", 7))
{
char*p=(char*)opt+7;
UINT32 mode=simple_strtoul(p, &p, 10);
primary_display_switch_dst_mode(mode%2);
return;
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = simple_strtoul(p, &p, 16);
unsigned long val = simple_strtoul(p + 1, &p, 16);
if (addr) {
OUTREG32(addr, val);
} else {
return;
}
}
else if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = (unsigned int) simple_strtoul(p, &p, 16);
if (addr) {
printk("Read register 0x%lx: 0x%08x\n", addr, INREG32(addr));
} else {
return;
}
}
else if (0 == strncmp(opt, "cmmva_dprec", 11))
{
dprec_handle_option(0x7);
}
else if (0 == strncmp(opt, "cmmpa_dprec", 11))
{
dprec_handle_option(0x3);
}
else if (0 == strncmp(opt, "dprec", 5))
{
char *p = (char *)opt + 6;
unsigned int option = (unsigned int) simple_strtoul(p, &p, 16);
dprec_handle_option(option);
}
else if (0 == strncmp(opt, "cmdq", 4))
{
char *p = (char *)opt + 5;
unsigned int option = (unsigned int) simple_strtoul(p, &p, 16);
if(option)
primary_display_switch_cmdq_cpu(CMDQ_ENABLE);
else
primary_display_switch_cmdq_cpu(CMDQ_DISABLE);
}
else if (0 == strncmp(opt, "maxlayer", 8))
{
char *p = (char *)opt + 9;
unsigned int maxlayer = (unsigned int) simple_strtoul(p, &p, 10);
if(maxlayer)
primary_display_set_max_layer(maxlayer);
else
DISPERR("can't set max layer to 0\n");
}
else if (0 == strncmp(opt, "primary_reset", 13))
{
primary_display_reset();
}
else if(0 == strncmp(opt, "esd_check", 9))
{
char *p = (char *)opt + 10;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
primary_display_esd_check_enable(enable);
}
else if(0 == strncmp(opt, "esd_recovery", 12))
{
primary_display_esd_recovery();
}
else if(0 == strncmp(opt, "lcm0_reset", 10))
{
#if 1
DISP_CPU_REG_SET(DISPSYS_CONFIG_BASE+0x150, 1);
msleep(10);
DISP_CPU_REG_SET(DISPSYS_CONFIG_BASE+0x150, 0);
msleep(10);
DISP_CPU_REG_SET(DISPSYS_CONFIG_BASE+0x150, 1);
#else
#if 0
mt_set_gpio_mode(GPIO106|0x80000000, GPIO_MODE_00);
mt_set_gpio_dir(GPIO106|0x80000000, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO106|0x80000000, GPIO_OUT_ONE);
msleep(10);
mt_set_gpio_out(GPIO106|0x80000000, GPIO_OUT_ZERO);
msleep(10);
mt_set_gpio_out(GPIO106|0x80000000, GPIO_OUT_ONE);
#endif
#endif
}
else if(0 == strncmp(opt, "lcm0_reset0", 11))
{
DISP_CPU_REG_SET(DDP_REG_BASE_MMSYS_CONFIG+0x150,0);
}
else if(0 == strncmp(opt, "lcm0_reset1", 11))
{
DISP_CPU_REG_SET(DDP_REG_BASE_MMSYS_CONFIG+0x150,1);
}
else if (0 == strncmp(opt, "cg", 2))
{
char *p = (char *)opt + 2;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
primary_display_enable_path_cg(enable);
}
else if (0 == strncmp(opt, "ovl2mem:", 8))
{
if (0 == strncmp(opt + 8, "on", 2))
switch_ovl1_to_mem(true);
else
switch_ovl1_to_mem(false);
}
else if (0 == strncmp(opt, "dump_layer:", 11))
{
if (0 == strncmp(opt + 11, "on", 2))
{
char *p = (char *)opt + 14;
gCapturePriLayerDownX = simple_strtoul(p, &p, 10);
gCapturePriLayerDownY = simple_strtoul(p+1, &p, 10);
gCapturePriLayerNum= simple_strtoul(p+1, &p, 10);
gCapturePriLayerEnable = 1;
gCaptureWdmaLayerEnable = 1;
if(gCapturePriLayerDownX==0)
gCapturePriLayerDownX = 20;
if(gCapturePriLayerDownY==0)
gCapturePriLayerDownY = 20;
printk("dump_layer En %d DownX %d DownY %d,Num %d",gCapturePriLayerEnable,gCapturePriLayerDownX,gCapturePriLayerDownY,gCapturePriLayerNum);
}
else if (0 == strncmp(opt + 11, "off", 3))
{
gCapturePriLayerEnable = 0;
gCaptureWdmaLayerEnable = 0;
gCapturePriLayerNum = OVL_LAYER_NUM;
printk("dump_layer En %d\n",gCapturePriLayerEnable);
}
}
#ifdef MTK_TODO
#error
if (0 == strncmp(opt, "hdmion", 6))
{
// hdmi_force_init();
}
else if (0 == strncmp(opt, "fps:", 4))
{
if (0 == strncmp(opt + 4, "on", 2)) {
dbg_opt.en_fps_log = 1;
} else if (0 == strncmp(opt + 4, "off", 3)) {
dbg_opt.en_fps_log = 0;
} else {
goto Error;
}
reset_fps_logger();
}
else if (0 == strncmp(opt, "tl:", 3))
{
if (0 == strncmp(opt + 3, "on", 2)) {
dbg_opt.en_touch_latency_log = 1;
} else if (0 == strncmp(opt + 3, "off", 3)) {
dbg_opt.en_touch_latency_log = 0;
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "black", 5))
{
mtkfb_clear_lcm();
}
else if (0 == strncmp(opt, "suspend", 4))
{
DISP_PanelEnable(FALSE);
DISP_PowerEnable(FALSE);
}
else if (0 == strncmp(opt, "resume", 4))
{
DISP_PowerEnable(TRUE);
DISP_PanelEnable(TRUE);
}
else if (0 == strncmp(opt, "lcm:", 4))
{
if (0 == strncmp(opt + 4, "on", 2)) {
DISP_PanelEnable(TRUE);
} else if (0 == strncmp(opt + 4, "off", 3)) {
DISP_PanelEnable(FALSE);
}
else if (0 == strncmp(opt + 4, "init", 4)) {
if (NULL != lcm_drv && NULL != lcm_drv->init) {
lcm_drv->init();
}
}else {
goto Error;
}
}
else if (0 == strncmp(opt, "cabc:", 5))
{
if (0 == strncmp(opt + 5, "ui", 2)) {
mtkfb_set_backlight_mode(1);
}else if (0 == strncmp(opt + 5, "mov", 3)) {
mtkfb_set_backlight_mode(3);
}else if (0 == strncmp(opt + 5, "still", 5)) {
mtkfb_set_backlight_mode(2);
}else {
goto Error;
}
}
else if (0 == strncmp(opt, "lcd:", 4))
{
if (0 == strncmp(opt + 4, "on", 2)) {
DISP_PowerEnable(TRUE);
} else if (0 == strncmp(opt + 4, "off", 3)) {
DISP_PowerEnable(FALSE);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "vsynclog:", 9))
{
if (0 == strncmp(opt + 9, "on", 2))
{
EnableVSyncLog = 1;
} else if (0 == strncmp(opt + 9, "off", 3))
{
EnableVSyncLog = 0;
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "layer", 5))
{
dump_layer_info();
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = simple_strtoul(p, &p, 16);
unsigned long val = simple_strtoul(p + 1, &p, 16);
if (addr) {
OUTREG32(addr, val);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
if (addr) {
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DBG", "Read register 0x%08x: 0x%08x\n", addr, INREG32(addr));
} else {
goto Error;
}
}
else if(0 == strncmp(opt, "bkl:", 4))
{
char *p = (char *)opt + 4;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DBG", "process_dbg_opt(), set backlight level = %d\n", level);
DISP_SetBacklight(level);
}
else if(0 == strncmp(opt, "dither:", 7))
{
unsigned lrs, lgs, lbs, dbr, dbg, dbb;
char *p = (char *)opt + 7;
lrs = (unsigned int) simple_strtoul(p, &p, 16);
p++;
lgs = (unsigned int) simple_strtoul(p, &p, 16);
p++;
lbs = (unsigned int) simple_strtoul(p, &p, 16);
p++;
dbr = (unsigned int) simple_strtoul(p, &p, 16);
p++;
dbg = (unsigned int) simple_strtoul(p, &p, 16);
p++;
dbb = (unsigned int) simple_strtoul(p, &p, 16);
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DBG", "process_dbg_opt(), %d %d %d %d %d %d\n", lrs, lgs, lbs, dbr, dbg, dbb);
}
else if (0 == strncmp(opt, "mtkfblog:", 9))
{
if (0 == strncmp(opt + 9, "on", 2)) {
mtkfb_log_enable(true);
} else if (0 == strncmp(opt + 9, "off", 3)) {
mtkfb_log_enable(false);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "displog:", 8))
{
if (0 == strncmp(opt + 8, "on", 2)) {
disp_log_enable(true);
} else if (0 == strncmp(opt + 8, "off", 3)) {
disp_log_enable(false);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "mtkfb_vsynclog:", 15))
{
if (0 == strncmp(opt + 15, "on", 2)) {
mtkfb_vsync_log_enable(true);
} else if (0 == strncmp(opt + 15, "off", 3)) {
mtkfb_vsync_log_enable(false);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "log:", 4))
{
if (0 == strncmp(opt + 4, "on", 2)) {
mtkfb_log_enable(true);
disp_log_enable(true);
} else if (0 == strncmp(opt + 4, "off", 3)) {
mtkfb_log_enable(false);
disp_log_enable(false);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "update", 6))
{
DISP_UpdateScreen(0, 0, DISP_GetScreenWidth(), DISP_GetScreenHeight());
}
else if (0 == strncmp(opt, "pan_disp", 8))
{
mtkfb_pan_disp_test();
}
else if (0 == strncmp(opt, "sem_cnt", 7))
{
mtkfb_show_sem_cnt();
}
else if (0 == strncmp(opt, "hang:", 5))
{
if (0 == strncmp(opt + 5, "on", 2)) {
mtkfb_hang_test(true);
} else if (0 == strncmp(opt + 5, "off", 3)) {
mtkfb_hang_test(false);
} else{
goto Error;
}
}
else if (0 == strncmp(opt, "cpfbonly:", 9))
{
if (0 == strncmp(opt + 9, "on", 2))
{
mtkfb_capture_fb_only(true);
}
else if (0 == strncmp(opt + 9, "off", 3))
{
mtkfb_capture_fb_only(false);
}
}
else if (0 == strncmp(opt, "esd:", 4))
{
if (0 == strncmp(opt + 4, "on", 2))
{
esd_recovery_pause(FALSE);
}
else if (0 == strncmp(opt + 4, "off", 3))
{
esd_recovery_pause(TRUE);
}
}
else if (0 == strncmp(opt, "HQA:", 4))
{
if (0 == strncmp(opt + 4, "NormalToFactory", 15))
{
mtkfb_switch_normal_to_factory();
}
else if (0 == strncmp(opt + 4, "FactoryToNormal", 15))
{
mtkfb_switch_factory_to_normal();
}
}
else if (0 == strncmp(opt, "mmp", 3))
{
init_mtkfb_mmp_events();
}
else if (0 == strncmp(opt, "dump_ovl:", 9))
{
if (0 == strncmp(opt + 9, "on", 2))
{
char *p = (char *)opt + 12;
gCaptureOvlDownX = simple_strtoul(p, &p, 10);
gCaptureOvlDownY = simple_strtoul(p+1, &p, 10);
gCaptureOvlThreadEnable = 1;
wake_up_process(captureovl_task);
}
else if (0 == strncmp(opt + 9, "off", 3))
{
gCaptureOvlThreadEnable = 0;
}
}
else if (0 == strncmp(opt, "dump_fb:", 8))
{
if (0 == strncmp(opt + 8, "on", 2))
{
char *p = (char *)opt + 11;
gCaptureFBDownX = simple_strtoul(p, &p, 10);
gCaptureFBDownY = simple_strtoul(p+1, &p, 10);
gCaptureFBPeriod = simple_strtoul(p+1, &p, 10);
gCaptureFBEnable = 1;
wake_up_interruptible(&gCaptureFBWQ);
}
else if (0 == strncmp(opt + 8, "off", 3))
{
gCaptureFBEnable = 0;
}
}
else
{
if (disphal_process_dbg_opt(opt))
goto Error;
}
return;
Error:
DISP_LOG_PRINT(ANDROID_LOG_INFO, "ERROR", "parse command error!\n\n%s", STR_HELP);
#endif
}
irqreturn_t disp_irq_handler(int irq, void *dev_id)
{
DISP_MODULE_ENUM module = DISP_MODULE_UNKNOWN;
unsigned long reg_val = 0;
unsigned int index = 0;
unsigned int mutexID = 0;
unsigned long reg_temp_val = 0;
DDPDBG("disp_irq_handler, irq=%d, module=%s \n", irq, disp_irq_module(irq));
MMProfileLogEx(ddp_mmp_get_events()->DDP_IRQ, MMProfileFlagStart, irq, 0);
//switch(irq)
{
if(irq==dispsys_irq[DISP_REG_DSI0])
{
module = DISP_MODULE_DSI0;
reg_val = (DISP_REG_GET(dsi_reg_va + 0xC) & 0xff);
if(atomic_read(&ESDCheck_byCPU) == 0)
{
reg_temp_val=reg_val&0xfffe;//rd_rdy don't clear and wait for ESD & Read LCM will clear the bit.
DISP_CPU_REG_SET(dsi_reg_va + 0xC, ~reg_temp_val);
}
else
{
DISP_CPU_REG_SET(dsi_reg_va + 0xC, ~reg_val);
}
MMProfileLogEx(ddp_mmp_get_events()->DSI_IRQ[0], MMProfileFlagPulse, reg_val, 0);
}
else if(irq==dispsys_irq[DISP_REG_OVL0] || irq==dispsys_irq[DISP_REG_OVL1])
{
index = (irq==dispsys_irq[DISP_REG_OVL0]) ? 0 : 1;
module= (irq==dispsys_irq[DISP_REG_OVL0]) ? DISP_MODULE_OVL0 : DISP_MODULE_OVL1;
reg_val = DISP_REG_GET(DISP_REG_OVL_INTSTA+index*DISP_OVL_INDEX_OFFSET);
if(reg_val&(1<<1))
{
DDPIRQ("IRQ: OVL%d frame done! \n",index);
ovl_complete_irq_cnt[index]++;
// update OVL addr
{
unsigned int i = 0;
if(index==0)
{
for(i=0;i<4;i++)
{
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON)&(0x1<<i))
MMProfileLogEx(ddp_mmp_get_events()->layer[i], MMProfileFlagPulse, DISP_REG_GET(DISP_REG_OVL_L0_ADDR+i*0x20), 0);
}
}
if(index==1)
{
for(i=0;i<4;i++)
{
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_OVL_INDEX_OFFSET)&(0x1<<i))
MMProfileLogEx(ddp_mmp_get_events()->ovl1_layer[i], MMProfileFlagPulse, DISP_REG_GET(DISP_REG_OVL_L0_ADDR+DISP_OVL_INDEX_OFFSET+i*0x20), 0);
}
}
}
}
if(reg_val&(1<<2))
{
//DDPERR("IRQ: OVL%d frame underrun! cnt=%d \n",index, cnt_ovl_underflow[index]++);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<3))
{
DDPIRQ("IRQ: OVL%d sw reset done\n",index);
}
if(reg_val&(1<<4))
{
DDPIRQ("IRQ: OVL%d hw reset done\n",index);
}
if(reg_val&(1<<5))
{
DDPERR("IRQ: OVL%d-L0 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<6))
{
DDPERR("IRQ: OVL%d-L1 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<7))
{
DDPERR("IRQ: OVL%d-L2 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<8))
{
DDPERR("IRQ: OVL%d-L3 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<9))
{
//DDPERR("IRQ: OVL%d-L0 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<10))
{
//DDPERR("IRQ: OVL%d-L1 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<11))
{
//DDPERR("IRQ: OVL%d-L2 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<12))
{
//DDPERR("IRQ: OVL%d-L3 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
//clear intr
if(reg_val&(0xf<<5))
{
ddp_dump_analysis(DISP_MODULE_CONFIG);
if(index==0)
{
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_COLOR0);
ddp_dump_analysis(DISP_MODULE_AAL);
ddp_dump_analysis(DISP_MODULE_RDMA0);
}
else
{
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_RDMA1);
ddp_dump_reg(DISP_MODULE_CONFIG);
}
}
DISP_CPU_REG_SET(DISP_REG_OVL_INTSTA+index*DISP_OVL_INDEX_OFFSET, ~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->OVL_IRQ[index], MMProfileFlagPulse, reg_val, 0);
if(reg_val&0x1e0)
{
MMProfileLogEx(ddp_mmp_get_events()->ddp_abnormal_irq, MMProfileFlagPulse, (index<<16)|reg_val, module<<24);
}
}
else if(irq==dispsys_irq[DISP_REG_WDMA0] || irq==dispsys_irq[DISP_REG_WDMA1])
{
index = (irq==dispsys_irq[DISP_REG_WDMA0]) ? 0 : 1;
module =(irq==dispsys_irq[DISP_REG_WDMA0]) ? DISP_MODULE_WDMA0 : DISP_MODULE_WDMA1;
reg_val = DISP_REG_GET(DISP_REG_WDMA_INTSTA+index*DISP_WDMA_INDEX_OFFSET);
if(reg_val&(1<<0))
{
DDPIRQ("IRQ: WDMA%d frame done!\n",index);
}
if(reg_val&(1<<1))
{
DDPERR("IRQ: WDMA%d underrun! cnt=%d\n",index,cnt_wdma_underflow[index]++);
disp_irq_log_module |= 1<<module;
}
//clear intr
DISP_CPU_REG_SET(DISP_REG_WDMA_INTSTA+index*DISP_WDMA_INDEX_OFFSET,~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->WDMA_IRQ[index], MMProfileFlagPulse, reg_val, DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE));
if(reg_val&0x2)
{
MMProfileLogEx(ddp_mmp_get_events()->ddp_abnormal_irq, MMProfileFlagPulse, (index<<16)|reg_val, cnt_wdma_underflow[index]|(module<<24));
}
}
else if(irq==dispsys_irq[DISP_REG_RDMA0] || irq==dispsys_irq[DISP_REG_RDMA1])
{
if(dispsys_irq[DISP_REG_RDMA0]==irq)
{
index = 0;
module = DISP_MODULE_RDMA0;
}
else if(dispsys_irq[DISP_REG_RDMA1]==irq)
{
index = 1;
module = DISP_MODULE_RDMA1;
}
reg_val = DISP_REG_GET(DISP_REG_RDMA_INT_STATUS+index*DISP_RDMA_INDEX_OFFSET);
if(reg_val&(1<<0))
{
DDPIRQ("IRQ: RDMA%d reg update done! \n",index);
}
if(reg_val&(1<<1))
{
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagStart, reg_val, DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR));
rdma_start_time[index]= sched_clock();
DDPIRQ("IRQ: RDMA%d frame start! \n",index);
rdma_start_irq_cnt[index]++;
// rdma start/end irq should equal, else need reset ovl
if(gResetRDMAEnable == 1 &&
is_hwc_enabled == 1 &&
index ==0 &&
primary_display_is_video_mode()==1 &&
rdma_start_irq_cnt[0] > rdma_done_irq_cnt[0]+3)
{
ovl_reset(DISP_MODULE_OVL0, NULL);
if(ovl_get_status()!=DDP_OVL1_STATUS_SUB)
{
ovl_reset(DISP_MODULE_OVL1, NULL);
}
rdma_done_irq_cnt[0] = rdma_start_irq_cnt[0];
DDPERR("warning: reset ovl!\n");
}
#ifdef CONFIG_MTK_SEGMENT_TEST
if(record_rdma_end_interval == 1)
{
if(rdma_end_begin_time == 0)
{
rdma_end_begin_time = sched_clock();
//printk("[display_test]====RDMA frame end time1:%lld\n",rdma_end_begin_time);
}
else
{
unsigned long long time_now = sched_clock();
//printk("[display_test]====RDMA frame end time2:%lld\n",time_now);
//printk("[display_test]====RDMA frame end time3:this=%lld,max=%lld,min=%lld\n",time_now - rdma_end_begin_time,rdma_end_max_interval,rdma_end_min_interval);
if((time_now - rdma_end_begin_time) > rdma_end_max_interval)
{
rdma_end_max_interval = time_now - rdma_end_begin_time;
}
if((time_now - rdma_end_begin_time) < rdma_end_min_interval)
{
rdma_end_min_interval = time_now - rdma_end_begin_time;
}
rdma_end_begin_time = time_now;
}
}
#endif
}
if(reg_val&(1<<2))
{
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagEnd, reg_val, 0);
rdma_end_time[index]= sched_clock();
DDPIRQ("IRQ: RDMA%d frame done! \n",index);
//rdma_done_irq_cnt[index] ++;
rdma_done_irq_cnt[index] = rdma_start_irq_cnt[index];
}
if(reg_val&(1<<3))
{
DDPERR("IRQ: RDMA%d abnormal! cnt=%d \n",index, cnt_rdma_abnormal[index]++);
disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<4))
{
DDPERR("IRQ: RDMA%d underflow! cnt=%d \n",index, cnt_rdma_underflow[index]++);
disp_irq_log_module |= 1<<module;
rdma_underflow_irq_cnt[index]++;
}
if(reg_val&(1<<5))
{
DDPIRQ("IRQ: RDMA%d target line! \n",index);
rdma_targetline_irq_cnt[index]++;
}
//clear intr
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_STATUS+index*DISP_RDMA_INDEX_OFFSET,~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->RDMA_IRQ[index], MMProfileFlagPulse, reg_val, 0);
if(reg_val&0x18)
{
MMProfileLogEx(ddp_mmp_get_events()->ddp_abnormal_irq, MMProfileFlagPulse, (index<<16)|reg_val, rdma_underflow_irq_cnt[index]|(cnt_rdma_abnormal[index]<<8)||(module<<24));
}
}
else if(irq==dispsys_irq[DISP_REG_COLOR])
{
}
else if(irq==dispsys_irq[DISP_REG_MUTEX])
{
// mutex0: perimary disp
// mutex1: sub disp
// mutex2: aal
module = DISP_MODULE_MUTEX;
reg_val = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTSTA) & 0x7C1F;
for(mutexID = 0; mutexID<5; mutexID++)
{
if(reg_val & (0x1<<mutexID))
{
DDPIRQ("IRQ: mutex%d sof!\n",mutexID);
MMProfileLogEx(ddp_mmp_get_events()->MUTEX_IRQ[mutexID], MMProfileFlagPulse, reg_val, 0);
}
if(reg_val & (0x1<<(mutexID+DISP_MUTEX_TOTAL)))
{
DDPIRQ("IRQ: mutex%d eof!\n",mutexID);
MMProfileLogEx(ddp_mmp_get_events()->MUTEX_IRQ[mutexID], MMProfileFlagPulse, reg_val, 1);
}
}
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTSTA, ~reg_val);
}
else if(irq==dispsys_irq[DISP_REG_AAL])
{
module = DISP_MODULE_AAL;
reg_val = DISP_REG_GET(DISP_AAL_INTSTA);
disp_aal_on_end_of_frame();
}
else if(irq==dispsys_irq[DISP_REG_CONFIG]) // MMSYS error intr
{
reg_val = DISP_REG_GET(DISP_REG_CONFIG_MMSYS_INTSTA) & 0x7;
if(reg_val&(1<<0))
{
DDPERR("MMSYS to MFG APB TX Error, MMSYS clock off but MFG clock on! \n");
}
if(reg_val&(1<<1))
{
DDPERR("MMSYS to MJC APB TX Error, MMSYS clock off but MJC clock on! \n");
}
if(reg_val&(1<<2))
{
DDPERR("PWM APB TX Error! \n");
}
DISP_CPU_REG_SET(DISP_REG_CONFIG_MMSYS_INTSTA, ~reg_val);
}
else
{
module = DISP_MODULE_UNKNOWN;
reg_val = 0;
DDPERR("invalid irq=%d \n ", irq);
}
}
disp_invoke_irq_callbacks(module, reg_val);
if(disp_irq_log_module!=0)
{
wake_up_interruptible(&disp_irq_log_wq);
}
MMProfileLogEx(ddp_mmp_get_events()->DDP_IRQ, MMProfileFlagEnd, irq, reg_val);
return IRQ_HANDLED;
}
///TODO: move each irq to module driver
irqreturn_t disp_irq_handler(int irq, void *dev_id)
{
DISP_MODULE_ENUM module = DISP_MODULE_UNKNOWN;
unsigned int reg_val = 0;
unsigned int index = 0;
unsigned int mutexID = 0;
//MMProfileLogEx(ddp_mmp_get_events()->DDP_IRQ, MMProfileFlagStart, irq, 0);
if(irq==dispsys_irq[DISP_REG_DSI0] || irq==dispsys_irq[DISP_REG_DSI1])
{
index = (irq == dispsys_irq[DISP_REG_DSI0]) ? 0 : 1;
module = (irq == dispsys_irq[DISP_REG_DSI0]) ? DISP_MODULE_DSI0 : DISP_MODULE_DSI1;
reg_val = DISP_REG_GET(DDP_REG_BASE_DSI0+0xC + index * DISP_DSI_INDEX_OFFSET) & 0xff;
DISP_CPU_REG_SET(DDP_REG_BASE_DSI0+0xC + index * DISP_DSI_INDEX_OFFSET, ~reg_val);
DDPIRQ("IRQ: DSI%d 0x%x!\n", index, reg_val);
//MMProfileLogEx(ddp_mmp_get_events()->DSI_IRQ[index], MMProfileFlagPulse, reg_val, 0);
}
else if(irq==dispsys_irq[DISP_REG_OVL0] || irq==dispsys_irq[DISP_REG_OVL1])
{
index = (irq == dispsys_irq[DISP_REG_OVL0]) ? 0 : 1;
module = (irq == dispsys_irq[DISP_REG_OVL0]) ? DISP_MODULE_OVL0 : DISP_MODULE_OVL1;
reg_val = DISP_REG_GET(DISP_REG_OVL_INTSTA + index * DISP_OVL_INDEX_OFFSET);
if(reg_val&(1<<1))
DDPIRQ("IRQ: OVL%d frame done!\n", index);
if (reg_val & (1 << 2)) {
DDPERR("IRQ: OVL%d frame underrun! cnt=%d\n", index,
cnt_ovl_underflow[index]++);
disp_irq_log_module |= 1<<module;
}
if (reg_val & (1 << 3)) {
DDPIRQ("IRQ: OVL%d sw reset done\n", index);
}
if (reg_val & (1 << 4)) {
DDPIRQ("IRQ: OVL%d hw reset done\n", index);
}
if (reg_val & (1 << 5)) {
DDPERR("IRQ: OVL%d-RDMA0 not complete untill EOF!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 6)) {
DDPERR("IRQ: OVL%d-RDMA1 not complete untill EOF!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 7)) {
DDPERR("IRQ: OVL%d-RDMA2 not complete untill EOF!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 8)) {
DDPERR("IRQ: OVL%d-RDMA3 not complete untill EOF!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 9)) {
DDPERR("IRQ: OVL%d-RDMA0 fifo underflow!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 10)) {
DDPERR("IRQ: OVL%d-RDMA1 fifo underflow!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 11)) {
DDPERR("IRQ: OVL%d-RDMA2 fifo underflow!\n", index);
disp_irq_log_module |= 1 << module;
}
if (reg_val & (1 << 12)) {
DDPERR("IRQ: OVL%d-RDMA3 fifo underflow!\n", index);
disp_irq_log_module |= 1 << module;
}
DISP_CPU_REG_SET(DISP_REG_OVL_INTSTA + index * DISP_OVL_INDEX_OFFSET, ~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->OVL_IRQ[index], MMProfileFlagPulse, reg_val, DISP_REG_GET(DISP_REG_OVL_INTSTA+index*DISP_OVL_INDEX_OFFSET));
}
else if(irq==dispsys_irq[DISP_REG_WDMA0] || irq==dispsys_irq[DISP_REG_WDMA1])
{
index = (irq==dispsys_irq[DISP_REG_WDMA0]) ? 0 : 1;
module =(irq==dispsys_irq[DISP_REG_WDMA0]) ? DISP_MODULE_WDMA0 : DISP_MODULE_WDMA1;
reg_val = DISP_REG_GET(DISP_REG_WDMA_INTSTA+index*DISP_WDMA_INDEX_OFFSET);
if (reg_val & (1 << 0)) {
DDPIRQ("IRQ: WDMA%d frame done!\n", index);
}
if (reg_val & (1 << 1)) {
DDPERR("IRQ: WDMA%d underrun! cnt=%d\n", index,
cnt_wdma_underflow[index]++);
disp_irq_log_module |= 1 << module;
}
DISP_CPU_REG_SET(DISP_REG_WDMA_INTSTA + index * DISP_WDMA_INDEX_OFFSET, ~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->WDMA_IRQ[index], MMProfileFlagPulse,
reg_val, DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE));
}
else if(irq==dispsys_irq[DISP_REG_RDMA0]
|| irq==dispsys_irq[DISP_REG_RDMA1]
|| irq==dispsys_irq[DISP_REG_RDMA2] )
{
if(dispsys_irq[DISP_REG_RDMA0]==irq)
{
index = 0;
module = DISP_MODULE_RDMA0;
}
else if(dispsys_irq[DISP_REG_RDMA1]==irq)
{
index = 1;
module = DISP_MODULE_RDMA1;
} else if (dispsys_irq[DISP_REG_RDMA2] == irq) {
index = 2;
module = DISP_MODULE_RDMA2;
}
reg_val = DISP_REG_GET(DISP_REG_RDMA_INT_STATUS+index*DISP_RDMA_INDEX_OFFSET);
if (reg_val & (1 << 0)) {
DDPIRQ("IRQ: RDMA%d reg update done!\n", index);
}
/* deal with end first */
if (reg_val & (1 << 2)) {
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagEnd, reg_val, 0);
rdma_end_time[index] = sched_clock();
DDPIRQ("IRQ: RDMA%d frame done!\n", index);
}
if (reg_val & (1 << 1)) {
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagStart, reg_val, 0);
MMProfileLogEx(ddp_mmp_get_events()->layer[0], MMProfileFlagPulse,
DISP_REG_GET(DISP_REG_OVL_L0_ADDR),
DISP_REG_GET(DISP_REG_OVL_SRC_CON) & 0x1);
MMProfileLogEx(ddp_mmp_get_events()->layer[1], MMProfileFlagPulse,
DISP_REG_GET(DISP_REG_OVL_L1_ADDR),
DISP_REG_GET(DISP_REG_OVL_SRC_CON) & 0x2);
MMProfileLogEx(ddp_mmp_get_events()->layer[2], MMProfileFlagPulse,
DISP_REG_GET(DISP_REG_OVL_L2_ADDR),
DISP_REG_GET(DISP_REG_OVL_SRC_CON) & 0x4);
MMProfileLogEx(ddp_mmp_get_events()->layer[3], MMProfileFlagPulse,
DISP_REG_GET(DISP_REG_OVL_L3_ADDR),
DISP_REG_GET(DISP_REG_OVL_SRC_CON) & 0x8);
rdma_start_time[index] = sched_clock();
DDPIRQ("IRQ: RDMA%d frame start!\n", index);
}
if (reg_val & (1 << 3)) {
DDPERR("IRQ: RDMA%d abnormal! cnt=%d\n", index,
cnt_rdma_abnormal[index]++);
disp_irq_log_module |= 1 << module;
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagPulse, reg_val, 0);
}
if (reg_val & (1 << 4)) {
MMProfileLogEx(ddp_mmp_get_events()->rdma_underflow, MMProfileFlagPulse,cnt_rdma_underflow, 0);
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagPulse, reg_val, 0);
DDPERR("IRQ: RDMA%d underflow! cnt=%d dsi0_cur(%d,%d)\n", index, cnt_rdma_underflow[index]++,
DISP_REG_GET(DDP_REG_BASE_DSI0+0x168), DISP_REG_GET(DDP_REG_BASE_DSI0+0x16C));
disp_irq_log_module |= module;
}
if (reg_val & (1 << 5)) {
DDPIRQ("IRQ: RDMA%d target line!\n", index);
}
/* clear intr */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_STATUS + index * DISP_RDMA_INDEX_OFFSET, ~reg_val);
}
else if(irq==dispsys_irq[DISP_REG_COLOR0] || irq==dispsys_irq[DISP_REG_COLOR1])
{
index = (irq == dispsys_irq[DISP_REG_COLOR0]) ? 0 : 1;
module = (irq == dispsys_irq[DISP_REG_COLOR0]) ? DISP_MODULE_COLOR0 : DISP_MODULE_COLOR1;
reg_val = 0;
}
else if(irq==dispsys_irq[DISP_REG_MM_MUTEX])
{
module = DISP_MODULE_MUTEX;
reg_val = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTSTA) & 0x7C1F;
for (mutexID = 0; mutexID < 5; mutexID++) {
if (reg_val & (0x1 << mutexID)) {
DDPIRQ("IRQ: mutex%d sof!\n", mutexID);
MMProfileLogEx(ddp_mmp_get_events()->MUTEX_IRQ[mutexID],
MMProfileFlagPulse, reg_val, 0);
}
}
if (reg_val & (0x1 << (mutexID + DISP_MUTEX_TOTAL))) {
DDPIRQ("IRQ: mutex%d eof!\n", mutexID);
MMProfileLogEx(ddp_mmp_get_events()->MUTEX_IRQ[mutexID],
MMProfileFlagPulse, reg_val, 1);
}
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTSTA, ~reg_val);
}
else if(irq==dispsys_irq[DISP_REG_AAL])
{
module = DISP_MODULE_AAL;
reg_val = DISP_REG_GET(DISP_AAL_INTSTA);
disp_aal_on_end_of_frame();
}
else
{
module = DISP_MODULE_UNKNOWN;
reg_val = 0;
DDPERR("invalid irq=%d\n ", irq);
}
disp_invoke_irq_callbacks(module, reg_val);
if (disp_irq_log_module != 0) {
wake_up_interruptible(&disp_irq_log_wq);
}
//MMProfileLogEx(ddp_mmp_get_events()->DDP_IRQ, MMProfileFlagEnd, irq, reg_val);
return IRQ_HANDLED;
}
static void process_dbg_debug(const char *opt)
{
unsigned int enable = 0;
static disp_session_config config;
char *p;
char *buf = dbg_buf + strlen(dbg_buf);
int ret;
p = (char *)opt + 6;
ret = kstrtoul(p, 10, (long unsigned int *)&enable);
if (ret)
pr_err("DISP/%s: errno %d\n", __func__, ret);
if (enable == 1) {
DDPMSG("[DDP] debug=1, trigger AEE\n");
/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
} else if (enable == 2) {
ddp_mem_test();
} else if (enable == 3) {
ddp_lcd_test();
} else if (enable == 4) {
DDPAEE("test enable=%d\n", enable);
sprintf(buf, "test enable=%d\n", enable);
} else if (enable == 5) {
if (gDDPError == 0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
} else if (enable == 6) {
unsigned int i = 0;
int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
pr_debug("dump path status:");
for (i = 0; i < module_num; i++)
pr_debug("%s-", ddp_get_module_name(modules[i]));
pr_debug("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for (i = 0; i < module_num; i++)
ddp_dump_analysis(modules[i]);
if (primary_display_is_decouple_mode()) {
ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
ddp_dump_analysis(DISP_MODULE_WDMA0);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
if (primary_display_is_decouple_mode()) {
ddp_dump_reg(DISP_MODULE_OVL0);
ddp_dump_reg(DISP_MODULE_OVL1);
ddp_dump_reg(DISP_MODULE_WDMA0);
}
for (i = 0; i < module_num; i++)
ddp_dump_reg(modules[i]);
} else if (enable == 7) {
if (dbg_log_level < 3)
dbg_log_level++;
else
dbg_log_level = 0;
pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
} else if (enable == 8) {
DDPDUMP("clock_mm setting:%u\n", DISP_REG_GET(DISP_REG_CONFIG_C11));
if ((DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000) != 0xff000000)
DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
DISP_REG_GET(DISP_REG_CONFIG_C11));
} else if (enable == 9) {
gOVLBackground = 0xFF0000FF;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 10) {
gOVLBackground = 0xFF000000;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 11) {
unsigned int i = 0;
char *buf_temp = buf;
for (i = 0; i < DISP_REG_NUM; i++) {
DDPDUMP("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
sprintf(buf_temp, "i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i,
ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
buf_temp += strlen(buf_temp);
}
} else if (enable == 12) {
if (gUltraEnable == 0)
gUltraEnable = 1;
else
gUltraEnable = 0;
pr_debug("DDP: gUltraEnable=%d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
} else if (enable == 13) {
int ovl_status = ovl_get_status();
config.type = DISP_SESSION_MEMORY;
config.device_id = 0;
disp_create_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
ovl_get_status());
} else if (enable == 14) {
int ovl_status = ovl_get_status();
disp_destroy_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
ovl_get_status());
} else if (enable == 15) {
/* extern smi_dumpDebugMsg(void); */
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_RDMA0);
ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
/* dump ultra/preultra related regs */
DDPMSG("wdma_con1(2c)=0x%x, wdma_con2(0x38)=0x%x,\n",
DISP_REG_GET(DISP_REG_WDMA_BUF_CON1),
DISP_REG_GET(DISP_REG_WDMA_BUF_CON2));
DDPMSG("rdma_gmc0(30)=0x%x, rdma_gmc1(38)=0x%x, fifo_con(40)=0x%x\n",
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
DDPMSG("ovl0_gmc: 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc: 0x%x, 0x%x, 0x%x, 0x%x,\n",
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET));
/* dump smi regs */
/* smi_dumpDebugMsg(); */
} else if (enable == 16) {
if (gDumpMemoutCmdq == 0)
gDumpMemoutCmdq = 1;
else
gDumpMemoutCmdq = 0;
pr_debug("DDP: gDumpMemoutCmdq=%d\n", gDumpMemoutCmdq);
sprintf(buf, "gDumpMemoutCmdq: %d\n", gDumpMemoutCmdq);
} else if (enable == 21) {
if (gEnableSODIControl == 0)
gEnableSODIControl = 1;
else
gEnableSODIControl = 0;
pr_debug("DDP: gEnableSODIControl=%d\n", gEnableSODIControl);
sprintf(buf, "gEnableSODIControl: %d\n", gEnableSODIControl);
} else if (enable == 22) {
if (gPrefetchControl == 0)
gPrefetchControl = 1;
else
gPrefetchControl = 0;
pr_debug("DDP: gPrefetchControl=%d\n", gPrefetchControl);
sprintf(buf, "gPrefetchControl: %d\n", gPrefetchControl);
} else if (enable == 23) {
if (disp_low_power_enlarge_blanking == 0)
disp_low_power_enlarge_blanking = 1;
else
disp_low_power_enlarge_blanking = 0;
pr_debug("DDP: disp_low_power_enlarge_blanking=%d\n",
disp_low_power_enlarge_blanking);
sprintf(buf, "disp_low_power_enlarge_blanking: %d\n",
disp_low_power_enlarge_blanking);
} else if (enable == 24) {
if (disp_low_power_disable_ddp_clock == 0)
disp_low_power_disable_ddp_clock = 1;
else
disp_low_power_disable_ddp_clock = 0;
pr_debug("DDP: disp_low_power_disable_ddp_clock=%d\n",
disp_low_power_disable_ddp_clock);
sprintf(buf, "disp_low_power_disable_ddp_clock: %d\n",
disp_low_power_disable_ddp_clock);
} else if (enable == 25) {
if (disp_low_power_disable_fence_thread == 0)
disp_low_power_disable_fence_thread = 1;
else
disp_low_power_disable_fence_thread = 0;
pr_debug("DDP: disp_low_power_disable_fence_thread=%d\n",
disp_low_power_disable_fence_thread);
sprintf(buf, "disp_low_power_disable_fence_thread: %d\n",
disp_low_power_disable_fence_thread);
} else if (enable == 26) {
if (disp_low_power_remove_ovl == 0)
disp_low_power_remove_ovl = 1;
else
disp_low_power_remove_ovl = 0;
pr_debug("DDP: disp_low_power_remove_ovl=%d\n", disp_low_power_remove_ovl);
sprintf(buf, "disp_low_power_remove_ovl: %d\n", disp_low_power_remove_ovl);
} else if (enable == 27) {
if (gSkipIdleDetect == 0)
gSkipIdleDetect = 1;
else
gSkipIdleDetect = 0;
pr_debug("DDP: gSkipIdleDetect=%d\n", gSkipIdleDetect);
sprintf(buf, "gSkipIdleDetect: %d\n", gSkipIdleDetect);
} else if (enable == 28) {
if (gDumpClockStatus == 0)
gDumpClockStatus = 1;
else
gDumpClockStatus = 0;
pr_debug("DDP: gDumpClockStatus=%d\n", gDumpClockStatus);
sprintf(buf, "gDumpClockStatus: %d\n", gDumpClockStatus);
} else if (enable == 29) {
if (gEnableUartLog == 0)
gEnableUartLog = 1;
else
gEnableUartLog = 0;
pr_debug("DDP: gEnableUartLog=%d\n", gEnableUartLog);
sprintf(buf, "gEnableUartLog: %d\n", gEnableUartLog);
} else if (enable == 30) {
if (gEnableMutexRisingEdge == 0) {
gEnableMutexRisingEdge = 1;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
DISP_REG_CONFIG_MUTEX0_SOF, 1);
} else {
gEnableMutexRisingEdge = 0;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
DISP_REG_CONFIG_MUTEX0_SOF, 0);
}
pr_debug("DDP: gEnableMutexRisingEdge=%d\n", gEnableMutexRisingEdge);
sprintf(buf, "gEnableMutexRisingEdge: %d\n", gEnableMutexRisingEdge);
} else if (enable == 31) {
if (gEnableReduceRegWrite == 0)
gEnableReduceRegWrite = 1;
else
gEnableReduceRegWrite = 0;
pr_debug("DDP: gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
sprintf(buf, "gEnableReduceRegWrite: %d\n", gEnableReduceRegWrite);
} else if (enable == 32) {
DDPAEE("DDP: (32)gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
} else if (enable == 33) {
if (gDumpConfigCMD == 0)
gDumpConfigCMD = 1;
else
gDumpConfigCMD = 0;
pr_debug("DDP: gDumpConfigCMD=%d\n", gDumpConfigCMD);
sprintf(buf, "gDumpConfigCMD: %d\n", gDumpConfigCMD);
} else if (enable == 34) {
if (gESDEnableSODI == 0)
gESDEnableSODI = 1;
else
gESDEnableSODI = 0;
pr_debug("DDP: gESDEnableSODI=%d\n", gESDEnableSODI);
sprintf(buf, "gESDEnableSODI: %d\n", gESDEnableSODI);
} else if (enable == 35) {
if (gEnableOVLStatusCheck == 0)
gEnableOVLStatusCheck = 1;
else
gEnableOVLStatusCheck = 0;
pr_debug("DDP: gEnableOVLStatusCheck=%d\n", gEnableOVLStatusCheck);
sprintf(buf, "gEnableOVLStatusCheck: %d\n", gEnableOVLStatusCheck);
} else if (enable == 36) {
if (gResetRDMAEnable == 0)
gResetRDMAEnable = 1;
else
gResetRDMAEnable = 0;
pr_debug("DDP: gResetRDMAEnable=%d\n", gResetRDMAEnable);
sprintf(buf, "gResetRDMAEnable: %d\n", gResetRDMAEnable);
} else if (enable == 37) {
unsigned int reg_value = 0;
if (gEnableIRQ == 0) {
gEnableIRQ = 1;
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
} else {
gEnableIRQ = 0;
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value & (~(1 << 0)) &
(~(1 << DISP_MUTEX_TOTAL)));
}
pr_debug("DDP: gEnableIRQ=%d\n", gEnableIRQ);
sprintf(buf, "gEnableIRQ: %d\n", gEnableIRQ);
} else if (enable == 38) {
if (gDisableSODIForTriggerLoop == 0)
gDisableSODIForTriggerLoop = 1;
else
gDisableSODIForTriggerLoop = 0;
pr_debug("DDP: gDisableSODIForTriggerLoop=%d\n",
gDisableSODIForTriggerLoop);
sprintf(buf, "gDisableSODIForTriggerLoop: %d\n",
gDisableSODIForTriggerLoop);
} else if (enable == 39) {
cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
sprintf(buf, "enable=%d\n", enable);
} else if (enable == 41) {
if (gResetOVLInAALTrigger == 0)
gResetOVLInAALTrigger = 1;
else
gResetOVLInAALTrigger = 0;
pr_debug("DDP: gResetOVLInAALTrigger=%d\n", gResetOVLInAALTrigger);
sprintf(buf, "gResetOVLInAALTrigger: %d\n", gResetOVLInAALTrigger);
} else if (enable == 42) {
if (gDisableOVLTF == 0)
gDisableOVLTF = 1;
else
gDisableOVLTF = 0;
pr_debug("DDP: gDisableOVLTF=%d\n", gDisableOVLTF);
sprintf(buf, "gDisableOVLTF: %d\n", gDisableOVLTF);
} else if (enable == 43) {
if (gDumpESDCMD == 0)
gDumpESDCMD = 1;
else
gDumpESDCMD = 0;
pr_debug("DDP: gDumpESDCMD=%d\n", gDumpESDCMD);
sprintf(buf, "gDumpESDCMD: %d\n", gDumpESDCMD);
} else if (enable == 44) {
/* extern void disp_dump_emi_status(void); */
disp_dump_emi_status();
sprintf(buf, "dump emi status!\n");
} else if (enable == 40) {
sprintf(buf, "version: %d, %s\n", 7, __TIME__);
} else if (enable == 45) {
ddp_aee_print("DDP AEE DUMP!!\n");
} else if (enable == 46) {
ASSERT(0);
} else if (enable == 47) {
if (gEnableDSIStateCheck == 0)
gEnableDSIStateCheck = 1;
else
gEnableDSIStateCheck = 0;
pr_debug("DDP: gEnableDSIStateCheck=%d\n", gEnableDSIStateCheck);
sprintf(buf, "gEnableDSIStateCheck: %d\n", gEnableDSIStateCheck);
} else if (enable == 48) {
if (gMutexFreeRun == 0)
gMutexFreeRun = 1;
else
gMutexFreeRun = 0;
pr_debug("DDP: gMutexFreeRun=%d\n", gMutexFreeRun);
sprintf(buf, "gMutexFreeRun: %d\n", gMutexFreeRun);
}
}