static void tmd20qvga_disp_set_display_area(word start_row, word end_row)
{
word start_driving = start_row;
word end_driving = end_row;
if (!disp_initialized)
return;
/* Range checking
*/
if (end_driving >= QVGA_HEIGHT)
end_driving = QVGA_HEIGHT - 1;
if (start_driving > end_driving) {
/* Probably Backwards Switch */
start_driving = end_driving;
end_driving = start_row; /* Has not changed */
if (end_driving >= QVGA_HEIGHT)
end_driving = QVGA_HEIGHT - 1;
}
if ((start_driving == disp_area_start_row)
&& (end_driving == disp_area_end_row))
return;
disp_area_start_row = start_driving;
disp_area_end_row = end_driving;
DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR,
DISP_VAL_IF(start_driving & 0x100,
DISP_BITMASK_SS18) |
DISP_VAL_IF(start_driving & 0x080,
DISP_BITMASK_SS17) |
DISP_VAL_IF(start_driving & 0x040,
DISP_BITMASK_SS16) |
DISP_VAL_IF(start_driving & 0x020,
DISP_BITMASK_SS15) |
DISP_VAL_IF(start_driving & 0x010,
DISP_BITMASK_SS14) |
DISP_VAL_IF(start_driving & 0x008,
DISP_BITMASK_SS13) |
DISP_VAL_IF(start_driving & 0x004,
DISP_BITMASK_SS12) |
DISP_VAL_IF(start_driving & 0x002,
DISP_BITMASK_SS11) |
DISP_VAL_IF(start_driving & 0x001, DISP_BITMASK_SS10));
DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR,
DISP_VAL_IF(end_driving & 0x100, DISP_BITMASK_SE18) |
DISP_VAL_IF(end_driving & 0x080, DISP_BITMASK_SE17) |
DISP_VAL_IF(end_driving & 0x040, DISP_BITMASK_SE16) |
DISP_VAL_IF(end_driving & 0x020, DISP_BITMASK_SE15) |
DISP_VAL_IF(end_driving & 0x010, DISP_BITMASK_SE14) |
DISP_VAL_IF(end_driving & 0x008, DISP_BITMASK_SE13) |
DISP_VAL_IF(end_driving & 0x004, DISP_BITMASK_SE12) |
DISP_VAL_IF(end_driving & 0x002, DISP_BITMASK_SE11) |
DISP_VAL_IF(end_driving & 0x001, DISP_BITMASK_SE10));
}
static void tmd20qvga_disp_set_contrast(void)
{
#if (defined(TMD20QVGA_LCD_18BPP))
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0302);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07);
#else
int newcontrast = 0x46;
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR,
DISP_VAL_IF(newcontrast & 0x0001,
DISP_BITMASK_PKP20) | DISP_VAL_IF(newcontrast
& 0x0002,
DISP_BITMASK_PKP21)
| DISP_VAL_IF(newcontrast & 0x0004,
DISP_BITMASK_PKP22) |
DISP_VAL_IF(newcontrast & 0x0010,
DISP_BITMASK_PKP30) | DISP_VAL_IF(newcontrast
& 0x0020,
DISP_BITMASK_PKP31)
| DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP32));
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR,
DISP_VAL_IF(newcontrast & 0x0010,
DISP_BITMASK_PKP40) | DISP_VAL_IF(newcontrast
& 0x0020,
DISP_BITMASK_PKP41)
| DISP_VAL_IF(newcontrast & 0x0040,
DISP_BITMASK_PKP42) |
DISP_VAL_IF(newcontrast & 0x0001,
DISP_BITMASK_PKP50) | DISP_VAL_IF(newcontrast
& 0x0002,
DISP_BITMASK_PKP51)
| DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP52));
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07);
#endif /* defined(TMD20QVGA_LCD_18BPP) */
} /* End disp_set_contrast */
static int tmd20qvga_disp_on(struct platform_device *pdev)
{
if (!disp_initialized)
tmd20qvga_disp_init(pdev);
if (!display_on) {
/* Deep Stand-by -> Stand-by */
DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR);
WAIT_MSEC(1);
DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR);
WAIT_MSEC(1);
DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR);
WAIT_MSEC(1);
/* OFF -> Deep Stan-By -> Stand-by */
/* let's change the state from "Stand-by" to "Sleep" */
DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0005);
WAIT_MSEC(1);
/* Sleep -> Displaying */
DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0001);
DISP_WRITE_OUT(DISP_DRIVER_OUTPUT_CTL_ADDR, 0x0127);
DISP_WRITE_OUT(DISP_LCD_DRIVING_SIG_ADDR, 0x200);
/* fast write mode */
DISP_WRITE_OUT(DISP_ENTRY_MODE_ADDR, 0x0130);
if (tmd20qvga_lcd_rev == 2)
DISP_WRITE_OUT(DISP_TMD_700_ADDR, 0x0003);
/* back porch = 14 + front porch = 2 --> 16 lines */
if (tmd20qvga_lcd_rev == 2) {
#ifdef TMD20QVGA_LCD_18BPP
/* 256k color */
DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0000);
#else
/* 65k color */
DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4000);
#endif
DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x0302);
} else {
#ifdef TMD20QVGA_LCD_18BPP
/* 256k color */
DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0004);
#else
/* 65k color */
DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4004);
#endif
DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x020E);
}
/* 16 bit one transfer */
if (tmd20qvga_lcd_rev == 2) {
DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010);
DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0302);
DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0102);
DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_TMD_015_ADDR, 0x2000);
DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0304);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0101);
DISP_WRITE_OUT(DISP_TMD_305_ADDR, 0);
DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F);
DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x077D);
DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0005);
DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0015);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC010);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x0001);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFFE);
WAIT_MSEC(60);
} else {
DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0001);
DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010);
DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0301);
DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0001);
DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0507);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0405);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0607);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0502);
DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0301);
DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F);
DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x0795);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0102);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0450);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0103);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0008);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0104);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0C00);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0105);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_7_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0106);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0801);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
WAIT_MSEC(1);
DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x001F);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101);
WAIT_MSEC(60);
DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x009F);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101);
WAIT_MSEC(10);
DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, 0x0010);
DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, 0x00FF);
DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, 0x0000);
DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, 0x013F);
/* RAM starts at address 0x10 */
DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, 0x0010);
DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, 0x0000);
/* lcd controller uses internal clock, not ext. vsync */
DISP_CMD_OUT(DISP_CMD_RAMWR);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0881);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BE1);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFF);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
}
display_on = TRUE;
}
return 0;
}
static int tmd20qvga_disp_off(struct platform_device *pdev)
{
if (!disp_initialized)
tmd20qvga_disp_init(pdev);
if (display_on) {
if (tmd20qvga_lcd_rev == 2) {
DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000A);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFEE);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xF812);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xE811);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC011);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x4011);
WAIT_MSEC(20);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0010);
} else {
DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000F);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFE);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BED);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
WAIT_MSEC(40);
DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x00CD);
DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
WAIT_MSEC(20);
DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0);
}
DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0004);
DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0000);
display_on = FALSE;
}
return 0;
}
