/* Identify NIC type */ static void identify_nic(void) { struct board_info *db = &dmfe_info; /* Point a board information structure */ u16 phy_reg3; DM9000_iow(DM9000_NCR, NCR_EXT_PHY); phy_reg3 = phy_read(3); switch (phy_reg3 & 0xfff0) { case 0xb900: if (phy_read(31) == 0x4404) { db->nic_type = HOMERUN_NIC; program_dm9801(phy_reg3); DM9000_DBG("found homerun NIC\n"); } else { db->nic_type = LONGRUN_NIC; DM9000_DBG("found longrun NIC\n"); program_dm9802(); } break; default: db->nic_type = FASTETHER_NIC; break; } DM9000_iow(DM9000_NCR, 0); }
/* Set PHY operationg mode */ static void set_PHY_mode(void) { u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000; if (!(media_mode & DM9000_AUTO)) { switch (media_mode) { case DM9000_10MHD: phy_reg4 = 0x21; phy_reg0 = 0x0000; break; case DM9000_10MFD: phy_reg4 = 0x41; phy_reg0 = 0x1100; break; case DM9000_100MHD: phy_reg4 = 0x81; phy_reg0 = 0x2000; break; case DM9000_100MFD: phy_reg4 = 0x101; phy_reg0 = 0x3100; break; } phy_write(4, phy_reg4); /* Set PHY media mode */ phy_write(0, phy_reg0); /* Tmp */ } DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ }
static u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); DM9000_iow(DM9000_EPCR, 0x4); udelay(200); DM9000_iow(DM9000_EPCR, 0x0); return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); }
/* Stop the interface. The interface is stopped when it is brought. */ void eth_halt(void) { DM9000_DBG("eth_halt\n"); /* RESET devie */ phy_write(0, 0x8000); /* PHY RESET */ DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ }
/* Hardware start transmission. Send a packet to media from the upper layer. */ int eth_send(volatile void *packet, int length) { char *data_ptr; u32 tmplen, i; int tmo; DM9000_DBG("eth_send: length: %d\n", length); for (i = 0; i < length; i++) { if (i % 8 == 0) DM9000_DBG("\nSend: 02x: ", i); DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); } DM9000_DBG("\n"); /* Move data to DM9000 TX RAM */ data_ptr = (char *) packet; DM9000_outb(DM9000_MWCMD, DM9000_IO); #ifdef CONFIG_DM9000_USE_8BIT /* Byte mode */ for (i = 0; i < length; i++) DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); #endif /* */ #ifdef CONFIG_DM9000_USE_16BIT tmplen = (length + 1) / 2; for (i = 0; i < tmplen; i++) DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); #endif /* */ #ifdef CONFIG_DM9000_USE_32BIT tmplen = (length + 3) / 4; for (i = 0; i < tmplen; i++) DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); #endif /* */ /* Set TX length to DM9000 */ DM9000_iow(DM9000_TXPLL, length & 0xff); DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); /* Issue TX polling command */ DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ /* wait for end of transmission */ tmo = get_timer(0) + 5 * CFG_HZ; while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { if (get_timer(0) >= tmo) { printf("transmission timeout\n"); break; } } DM9000_DBG("transmit done\n\n"); return 0; }
/* Write a word to phyxcer */ static void phy_write(int reg, u16 value) { /* Fill the phyxcer register into REG_0C */ DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); /* Fill the written data into REG_0D & REG_0E */ DM9000_iow(DM9000_EPDRL, (value & 0xff)); DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ udelay(500); /* Wait write complete */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); }
/* Read a word from phyxcer */ static u16 phy_read(int reg) { u16 val; /* Fill the phyxcer register into REG_0C */ DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ udelay(100); /* Wait read complete */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); /* The read data keeps on REG_0D & REG_0E */ DM9000_DBG("phy_read(%d): %d\n", reg, val); return val; }
/* General Purpose dm9000 reset routine */ static void dm9000_reset(void) { DM9000_DBG("resetting\n"); DM9000_iow(DM9000_NCR, NCR_RST); udelay(1000); /* delay 1ms */ }
/* Received a packet and pass to upper layer */ int eth_rx(void) { u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; u16 RxStatus, RxLen = 0; u32 tmplen, i; #ifdef CONFIG_DM9000_USE_32BIT u32 tmpdata; #endif /* Check packet ready or not */ DM9000_ior(DM9000_MRCMDX); /* Dummy read */ rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ if (rxbyte == 0) return 0; /* Status check: this byte must be 0 or 1 */ if (rxbyte > 1) { DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ DM9000_DBG("rx status check: %d\n", rxbyte); } DM9000_DBG("receiving packet\n"); /* A packet ready now & Get status/length */ DM9000_outb(DM9000_MRCMD, DM9000_IO); #ifdef CONFIG_DM9000_USE_8BIT RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); #endif /* */ #ifdef CONFIG_DM9000_USE_16BIT RxStatus = DM9000_inw(DM9000_DATA); RxLen = DM9000_inw(DM9000_DATA); #endif /* */ #ifdef CONFIG_DM9000_USE_32BIT tmpdata = DM9000_inl(DM9000_DATA); RxStatus = tmpdata; RxLen = tmpdata >> 16; #endif /* */ DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); /* Move data from DM9000 */ /* Read received packet from RX SRAM */ #ifdef CONFIG_DM9000_USE_8BIT for (i = 0; i < RxLen; i++) rdptr[i] = DM9000_inb(DM9000_DATA); #endif /* */ #ifdef CONFIG_DM9000_USE_16BIT tmplen = (RxLen + 1) / 2; for (i = 0; i < tmplen; i++) ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); #endif /* */ #ifdef CONFIG_DM9000_USE_32BIT tmplen = (RxLen + 3) / 4; for (i = 0; i < tmplen; i++) ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); #endif /* */ if ((RxStatus & 0xbf00) || (RxLen < 0x40) || (RxLen > DM9000_PKT_MAX)) { if (RxStatus & 0x100) { printf("rx fifo error\n"); } if (RxStatus & 0x200) { printf("rx crc error\n"); } if (RxStatus & 0x8000) { printf("rx length error\n"); } if (RxLen > DM9000_PKT_MAX) { printf("rx length too big\n"); dm9000_reset(); } } else { /* Pass to upper layer */ DM9000_DBG("passing packet to upper layer\n"); NetReceive(NetRxPackets[0], RxLen); return RxLen; } return 0; }
/* Initilize dm9000 board */ int eth_init(bd_t * bd) { int i, oft; DM9000_DBG("eth_init()\n"); /* RESET device */ dm9000_reset(); dm9000_probe(); /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ identify_nic(); /* GPIO0 on pre-activate PHY */ DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ /* Set PHY */ set_PHY_mode(); /* Program operating register */ DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ /* Set Node address */ //HJ_start /* www.embedsky.net */ char *tmp = getenv("ethaddr"); char *end; for (i = 0; i < 6; i++) { bd->bi_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; if(tmp) tmp = (*end) ? end+1 : end; } //HJ_end /* www.embedsky.net */ printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_iow(oft, bd->bi_enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); /* read back mac, just to be sure */ for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_DBG("%02x:", DM9000_ior(oft)); DM9000_DBG("\n"); /* Activate DM9000 */ DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ return 0; }
/* Initilize dm9000 board */ int eth_init(bd_t * bd) { int i, oft, lnk; DM9000_DBG("eth_init()\n"); /* RESET device */ dm9000_reset(); dm9000_probe(); /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ identify_nic(); /* GPIO0 on pre-activate PHY */ DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ /* Set PHY */ set_PHY_mode(); /* Program operating register */ DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ /* Set Node address */ // for (i = 0; i < 6; i++) //raymanfeng- // ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_iow(oft, bd->bi_enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); /* read back mac, just to be sure */ for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_DBG("%02x:", DM9000_ior(oft)); DM9000_DBG("\n"); /* Activate DM9000 */ DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ /* //raymanfeng- i = 0; while (!(phy_read(1) & 0x20)) { // autonegation complete bit udelay(1000); i++; if (i == 10000) { printf("could not establish link\n"); return 0; } } // see what we've got lnk = phy_read(17) >> 12; printf("operating at "); switch (lnk) { case 1: printf("10M half duplex "); break; case 2: printf("10M full duplex "); break; case 4: printf("100M half duplex "); break; case 8: printf("100M full duplex "); break; default: printf("unknown: %d ", lnk); break; } printf("mode\n"); */ return 0; }