/* Do a DMA transfer M2M, M2P,P2M or P2P */
void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size)
{
GPDMA_Channel_CFG_Type GPDMACfg;
uint8_t SrcPeripheral = 0, DstPeripheral = 0;
GPDMACfg.ChannelNum = ChannelNum;
GPDMACfg.TransferType = TransferType;
GPDMACfg.TransferSize = Size;
switch (TransferType) {
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
GPDMACfg.SrcAddr = (uint32_t) src;
GPDMACfg.DstAddr = (uint32_t) dst;
src = 0;
dst = 0;
GPDMACfg.TransferWidth = GPDMA_WIDTH_BYTE;
break;
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
GPDMACfg.SrcAddr = (uint32_t) src;
src = 0;
GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
DstPeripheral = DMAMUX_Config(dst);
break;
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
GPDMACfg.DstAddr = (uint32_t) dst;
SrcPeripheral = DMAMUX_Config(src);
dst = 0;
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
SrcPeripheral = DMAMUX_Config(src);
DstPeripheral = DMAMUX_Config(dst);
break;
default:
break;
}
IP_GPDMA_Setup(LPC_GPDMA, &GPDMACfg, (uint32_t) GPDMA_LUTPerBurst[src], (uint32_t) GPDMA_LUTPerBurst[dst],
(uint32_t) GPDMA_LUTPerWid[src], (uint32_t) GPDMA_LUTPerWid[dst], (uint32_t) GPDMA_LUTPerAddr[src],
(uint32_t) GPDMA_LUTPerAddr[dst], SrcPeripheral, DstPeripheral);
/* Start the Channel */
IP_GPDMA_ChannelCmd(LPC_GPDMA, ChannelNum, ENABLE);
}
/* Do a DMA transfer M2M, M2P,P2M or P2P */
Status Chip_DMA_Transfer(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum,
uint32_t src,
uint32_t dst,
IP_GPDMA_FLOW_CONTROL_T TransferType,
uint32_t Size)
{
GPDMA_Channel_CFG_T GPDMACfg;
uint8_t SrcPeripheral = 0, DstPeripheral = 0;
uint32_t cwrd;
int ret;
ret = Chip_DMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, Size, TransferType);
if (ret < 0) {
return ERROR;
}
/* Adjust src/dst index if they are memory */
if (ret & 1) {
src = 0;
}
else {
SrcPeripheral = DMAMUX_Config(src);
}
if (ret & 2) {
dst = 0;
}
else {
DstPeripheral = DMAMUX_Config(dst);
}
cwrd = IP_GPDMA_MakeCtrlWord(&GPDMACfg,
(uint32_t) GPDMA_LUTPerBurst[src],
(uint32_t) GPDMA_LUTPerBurst[dst],
(uint32_t) GPDMA_LUTPerWid[src],
(uint32_t) GPDMA_LUTPerWid[dst]);
if (IP_GPDMA_Setup(pGPDMA, &GPDMACfg, cwrd, 0, SrcPeripheral, DstPeripheral) == ERROR) {
return ERROR;
}
/* Start the Channel */
IP_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE);
return SUCCESS;
}
/* Do a DMA scatter-gather transfer M2M, M2P,P2M or P2P using DMA descriptors */
Status Chip_DMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum,
const DMA_TransferDescriptor_t *DMADescriptor,
IP_GPDMA_FLOW_CONTROL_T TransferType)
{
const DMA_TransferDescriptor_t *dsc = DMADescriptor;
GPDMA_Channel_CFG_T GPDMACfg;
uint8_t SrcPeripheral = 0, DstPeripheral = 0;
uint32_t src = DMADescriptor->src, dst = DMADescriptor->dst;
int ret;
ret = Chip_DMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, 0, TransferType);
if (ret < 0) {
return ERROR;
}
/* Adjust src/dst index if they are memory */
if (ret & 1) {
src = 0;
}
else {
SrcPeripheral = DMAMUX_Config(src);
}
if (ret & 2) {
dst = 0;
}
else {
DstPeripheral = DMAMUX_Config(dst);
}
if (IP_GPDMA_Setup(pGPDMA, &GPDMACfg, dsc->ctrl, dsc->lli, SrcPeripheral, DstPeripheral) == ERROR) {
return ERROR;
}
/* Start the Channel */
IP_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE);
return SUCCESS;
}
/********************************************************************//**
* @brief Setup GPDMA channel peripheral according to the specified
* parameters in the GPDMAChannelConfig.
* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure
* that contains the configuration information for the specified
* GPDMA channel peripheral.
* @return Setup status, could be:
* - ERROR :if selected channel is enabled before
* - SUCCESS :if channel is configured successfully
*********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
LPC_GPDMACH_TypeDef *pDMAch;
uint8_t SrcPeripheral=0, DestPeripheral=0;
if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
// This channel is enabled, return ERROR, need to release this channel first
return ERROR;
}
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
// Reset the Interrupt status
LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
// Clear DMA configure
pDMAch->CControl = 0x00;
pDMAch->CConfig = 0x00;
/* Assign Linker List Item value */
pDMAch->CLLI = GPDMAChannelConfig->DMALLI;
/* Set value to Channel Control Registers */
switch (GPDMAChannelConfig->TransferType)
{
// Memory to memory
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
// Assign physical source and destination address
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Memory to peripheral
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
// Assign physical source
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_I;
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
break;
// Peripheral to memory
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign memory destination address
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
break;
// Peripheral to peripheral
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
//to be defined
// Do not support any more transfer type, return ERROR
default:
return ERROR;
}
/* Enable DMA channels, little endian */
LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;
while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));
// Configure DMA Channel, enable Error Counter and Terminate counter
pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \
| GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);
return SUCCESS;
}
