Example #1
0
//------------------------------------------------------------------------------------------------------
// void rxCallBack(...)
//
//  Description:
//      This function is called by the interrupt routine when the Rx DMA channel
//      finishes the data transfer. The received packet's destination address
//      is checked. If not addressed to this node, or if the CRC value is not
//      correct, the packet is erased. An ACK is sent if the packet
//      tells to. A user defined callback function may is run if set (set
//      with setRxCallBackFunction())
//
//  Arguments:
//      void
//
//  Return value:
//      void
//-----------------------------------------------------------------------------
void rxCallBack(void)
{
   SPP_STRUCT __xdata* receivedPacket;
   BYTE res = FALSE;


   // Investigating the received packet.
   // Checking the destination address and that the CRC is OK.
   // The message is ACK'ed if it tells to.
   receivedPacket = (SPP_STRUCT __xdata*) GET_DMA_DEST(dmaRx);
   receivedPacket->payloadLength = receivedPacket->payloadLength-SPP_HEADER_AND_FOOTER_LENGTH;

   if((receivedPacket->destAddress == myAddress) || (receivedPacket->destAddress == BROADCAST_ADDRESS))
   {
      if(receivedPacket->payload[receivedPacket->payloadLength+1] & 0x80)
      {
         if(receivedPacket->flags == ACK)
         {
            res = ackReceived(receivedPacket->srcAddress);
         }
         else
         {
            sppRxStatus = PACKET_RECEIVED;
            res = TRUE;
            if(receivedPacket->flags & DO_ACK)
            {
               sendAck(receivedPacket);
            }
            sppRxStatus = RX_COMPLETE;
            if(rxCallBackFunction)
            {
               rxCallBackFunction();
            }
         }
      }
   }

   if(res == FALSE)
   {

      // rearming DMA channel
      DMA_ARM_CHANNEL(dmaNumberRx);
      RFIM |= IRQ_SFD;
      sppRxStatus = RX_WAIT;
   }
   return;
}   // ends rxCallBack
Example #2
0
__interrupt void spp_rf_IRQ(void)
{
   BYTE enabledAndActiveInterrupt;

   INT_GLOBAL_ENABLE(INT_OFF);
   enabledAndActiveInterrupt = RFIF;
   RFIF = 0x00;                        // Clear all interrupt flags
   INT_SETFLAG(INUM_RF, INT_CLR);    // Clear MCU interrupt flag
   enabledAndActiveInterrupt &= RFIM;

   // Start of frame delimiter (SFD)
   if(enabledAndActiveInterrupt & IRQ_SFD)
   {
      if(sppRxStatus == RX_WAIT)
      {
         sppRxStatus = RX_IN_PROGRESS;
         RFIM &= ~IRQ_SFD;
      }
   }

   // Transmission of a packet is finished. Enabling reception of ACK if required.
   if(enabledAndActiveInterrupt & IRQ_DONE)
   {
      if(sppTxStatus == TX_IN_PROGRESS)
      {
         if(pAckData == NULL)
         {
            sppTxStatus = TX_SUCCESSFUL;
         }
         else
         {
            DMA_ARM_CHANNEL(dmaNumberRx);
         }
      }

      // Clearing the tx done interrupt enable
      RFIM &= ~IRQ_DONE;

   }
   INT_GLOBAL_ENABLE(INT_ON);
}
Example #3
0
//-----------------------------------------------------------------------------
// See cul.h for a description of this function.
//-----------------------------------------------------------------------------
void sppReceive(SPP_STRUCT* pReceiveData){

   sppRxStatus = RX_WAIT;

   DMA_ABORT_CHANNEL(dmaNumberRx);
   // Setting the address to where the received data are to be written. // Setting max number of bytes to receive
   SET_DMA_DEST(dmaRx,pReceiveData);
   SET_DMA_LENGTH(dmaRx,255);

   // Arming the DMA channel. The receiver will initate the transfer when a packet is received.
   DMA_ARM_CHANNEL(dmaNumberRx);

   // Debug:
   SIDLE();

   RFIF &= ~IRQ_SFD;
   RFIM |= IRQ_SFD;
   // Turning on the receiver
   SRX();

   return;
}
Example #4
0
////////////////////////////////////////////////////////////////////////////////
/// @brief	Application main function.
////////////////////////////////////////////////////////////////////////////////
void main(void) {

  // Initializations
  SET_MAIN_CLOCK_SOURCE(CRYSTAL);
  SET_MAIN_CLOCK_SPEED(MHZ_26);
  CLKCON = (CLKCON & 0xC7);

  init_peripherals();
  
  P0 &= ~0x40;                            // Pulse the Codec Reset line (high to low, low to high)
  P0 |= 0x40;
  
  init_codec();                           // Initilize the Codec
  
  INT_SETFLAG(INUM_DMA, INT_CLR);         // clear the DMA interrupt flag
  I2SCFG0 |= 0x01;                        // Enable the I2S interface

  DMA_SET_ADDR_DESC0(&DmaDesc0);          // Set up DMA configuration table for channel 0
  DMA_SET_ADDR_DESC1234(&DmaDesc1_4[0]);  // Set up DMA configuration table for channels 1 - 4
  dmaMemtoMem(AF_BUF_SIZE);               // Set up DMA Channel 0 for memmory to memory data transfers
  initRf();                               // Set radio base frequency and reserve DMA channels 1 and 2 for RX/TX buffers
  dmaAudio();                             // Set up DMA channels 3 and 4 for the Audio In/Out buffers
  DMAIRQ = 0;
  DMA_ARM_CHANNEL(4);                     // Arm DMA channel 4

  macTimer3Init();

  INT_ENABLE(INUM_T1, INT_ON);            // Enable Timer 1 interrupts
  INT_ENABLE(INUM_DMA, INT_ON);           // Enable DMA interrupts
  INT_GLOBAL_ENABLE(INT_ON);              // Enable Global interrupts

  MAStxData.macPayloadLen = TX_PAYLOAD_LEN;
  MAStxData.macField = MAC_ADDR;

  while (1)  {        // main program loop
    setChannel(channel[band][ActiveChIdx]);             // SetChannel will set the MARCSTATE to IDLE
    ActiveChIdx = (ActiveChIdx + 1) & 0x03;
    
    SCAL();           // Start PLL calibration at new channel

    if ((P1 & 0x08) != aux_option_status) {             // if the 'SEL AUX IN' option bit has changed state
      if ((P1 & 0x08) == 0) {                           // SEL AUX IN has changed state to true
        I2Cwrite(MIC1LP_LEFTADC, 0xFC);                 // Disconnect MIC1LP/M from the Left ADC, Leave Left DAC enabled
        I2Cwrite(MIC2L_MIC2R_LEFTADC, 0x2F);            // Connect AUX In (MIC2L) to Left ADC
        I2Cwrite(LEFT_ADC_PGA_GAIN, 0x00);              // Set PGA gain to 0 dB
        aux_option_status &= ~0x08;
      }
      else {                                            // SEL AUX IN has changed state to false
        I2Cwrite(MIC2L_MIC2R_LEFTADC, 0xFF);            // Disconnect AUX In (MIC2L) from Left ADC
        I2Cwrite(MIC1LP_LEFTADC, 0x84);                 // Connect the internal microphone to the Left ADC using differential inputs (gain = 0 dB); Power Up the Left ADC
        I2Cwrite(LEFT_ADC_PGA_GAIN, 0x3C);              // Enable PGA and set gain to 30 dB
        aux_option_status |= 0x08;
      }
    }
     
    if ((P1 & 0x04) != agc_option_status) {             // if the 'ENA AGC' option bit has changed state
      if ((P1 & 0x04) == 0) {                           // ENA AGC has changed state to true
        I2Cwrite(LEFT_AGC_CNTRL_A, 0x90);               // Left AGC Control Register A - Enable, set target level to -8 dB
        I2Cwrite(LEFT_AGC_CNTRL_B, 0xC8);               // Left AGC Control Register B - Set maximum gain to  to 50 dB
        I2Cwrite(LEFT_AGC_CNTRL_C, 0x00);               // Left AGC Control Register C - Disable Silence Detection
        agc_option_status &= ~0x04;
      }
      else {                                            // SEL AUX IN has changed state to false
        I2Cwrite(LEFT_AGC_CNTRL_A, 0x10);               // Left AGC Control Register A - Disable
        agc_option_status |= 0x04;
      }    
    }
    
// Check the band selection bits

    band = 2;                             // if the switch is not in position 1 or 2, in must be in position 3
    
    if ((P1 & 0x10) == 0)                 // check if switch is in position 1
      band = 0;
    
    else if ((P0 & 0x04) == 0)            // check if switch is in position 2
      band = 1;
    
// Now wait for the "audio frame ready" signal

    while (audioFrameReady == FALSE);     // Wait until an audioframe is ready to be transmitted
    
    audioFrameReady = FALSE;              // Reset the flag

// Move data from the CODEC (audioOut) buffer to the TX buffer using DMA Channel 0

    SET_WORD(DmaDesc0.SRCADDRH, DmaDesc0.SRCADDRL, audioOut[activeOut]);
    SET_WORD(DmaDesc0.DESTADDRH, DmaDesc0.DESTADDRL, MAStxData.payload);
    DmaDesc0.SRCINC = SRCINC_1;           // Increment Source address 
    DMAARM |= DMA_CHANNEL_0;
    DMAREQ |= DMA_CHANNEL_0;              // Enable memory-to-memory transfer using DMA channel 0
    while ((DMAARM & DMA_CHANNEL_0) > 0); // Wait for transfer to complete

    while (MARCSTATE != 0x01);            // Wait for calibration to complete
   
    P2 |= 0x08;                   // Debug - Set P2_3 (TP2)
    rfSendPacket(MASTER_TX_TIMEOUT_WO_CALIB);
    P2 &= ~0x08;                  // Debug - Reset P2_3 (TP2)
  
  }   // end of 'while (1)' loop
}
Example #5
0
void dma_main(void){
#else
void main(void){
#endif
   DMA_DESC dmaChannel;
   char sourceString[56] = "This is a test string used to demonstrate DMA transfer."; //56 bytes
   char destString[56];
   INT8 i;
   INT8 errors = 0;


   initDma();



   //Clearing the destination
   memset(destString,0,sizeof(destString));

     // Setting up the DMA channel.
   SET_WORD(dmaChannel.SRCADDRH, dmaChannel.SRCADDRL,   &sourceString); // The start address of the data to be transmitted
   SET_WORD(dmaChannel.DESTADDRH, dmaChannel.DESTADDRL, &destString);   // The start address of the destination.
   SET_WORD(dmaChannel.LENH, dmaChannel.LENL, sizeof(sourceString));    // Setting the number of bytes to transfer.
   dmaChannel.VLEN      = VLEN_USE_LEN;  // Using the length field to determine how many bytes to transfer.
   dmaChannel.PRIORITY  = PRI_HIGH;      // High priority.
   dmaChannel.M8        = M8_USE_8_BITS; // Irrelevant since length is determined by the LENH and LENL.
   dmaChannel.IRQMASK   = FALSE;         // The DMA shall not issue an IRQ upon completion.
   dmaChannel.DESTINC   = DESTINC_1;     // The destination address is to be incremented by 1 after each transfer.
   dmaChannel.SRCINC    = SRCINC_1;      // The source address inremented by 1 byte after each transfer.
   dmaChannel.TRIG      = DMATRIG_NONE;  // The DMA channel will be started manually.
   dmaChannel.TMODE     = TMODE_BLOCK;   // The number of bytes specified by LENH and LENL is transferred.
   dmaChannel.WORDSIZE  = WORDSIZE_BYTE; // One byte is transferred each time.


   // Using DMA channel 0.
   // Setting where the DMA channel is to read the desciptor and arming the DMA channel.
   DMA_SET_ADDR_DESC0(&dmaChannel);
   DMA_ABORT_CHANNEL(0);
   DMA_ARM_CHANNEL(0);

   //Waiting for the user to start the transfer.
   lcdUpdate((char*)"Press S1",(char*)"to start DMA.");
   while(!buttonPushed());


   // Clearing all DMA complete flags and starting the transfer.
   DMAIRQ = 0x00;
   DMA_START_CHANNEL(0);

   // Waiting for the DMA to finish.
   while(!(DMAIRQ & DMA_CHANNEL_0));




   // Verifying that data is transferred correctly
   for(i=0;i<sizeof(sourceString);i++)
   {
     if(sourceString[i] != destString[i])
         errors++;
   }


   //Displaying the result
   if(errors == 0)
   {lcdUpdate((char*)"Dma transfer",(char*)"correct!");}
   else
   {lcdUpdate((char*)"Error in DMA",(char*)"Transfer");}



   haltApplicationWithLED();
   return;
}
Example #6
0
//-----------------------------------------------------------------------------
// See cul.h for a description of this function.
//-----------------------------------------------------------------------------
BYTE sppSend(SPP_STRUCT* pPacketPointer){
   BYTE res = TRUE;

   // Checking that length is not too long
   if (pPacketPointer->payloadLength > SPP_MAX_PAYLOAD_LENGTH)
   {
      res = TOO_LONG;
      sppTxStatus = TX_IDLE;
   }

   // Flipping the sequence bit, writing  total packet length and address if the transfer is not a retransmission.
   // If it is a retransmission, the fields are correct
   if(!(pPacketPointer->flags & RETRANSMISSION))
   {
      pPacketPointer->flags ^= SEQUENCE_BIT;
      pPacketPointer->payloadLength += SPP_HEADER_AND_FOOTER_LENGTH;
      pPacketPointer->srcAddress = myAddress;
   }


   // Setting up the DMA
   DMA_ABORT_CHANNEL(dmaNumberTx);
   SET_DMA_SOURCE(dmaTx,pPacketPointer);


   // Proceed if the packet length is OK.
   if (res == TRUE)
   {
      // Clearing RF interrupt flags and enabling RF interrupts.
      RFIF &= ~IRQ_DONE;
      RFIM &= ~IRQ_SFD;
      INT_SETFLAG(INUM_RF, INT_CLR);
#ifdef CCA_ENABLE
      if(!CCA)
      {
         SRX();
         // Turning on Rx and waiting to make the RSSI value become valid.
         halWait(1);
      }
      if(CCA)
#endif
      {  // Setting up radio
         DMA_ABORT_CHANNEL(dmaNumberRx);
         SIDLE();
         RFTXRXIF = 0;
         INT_GLOBAL_ENABLE(FALSE);
         DMA_ARM_CHANNEL(dmaNumberTx);
         STX();
         INT_GLOBAL_ENABLE(TRUE);
         sppTxStatus = TX_IN_PROGRESS;

         if(pPacketPointer->flags & DO_ACK)
         {
            pAckData = pPacketPointer;
            waitForAck();
         }
         else
         {
            pAckData = NULL;
         }
         RFIM |= IRQ_DONE;
      }
#ifdef CCA_ENABLE
      // The "air" is busy
      else
      {
         res = CHANNEL_BUSY;
         RFIM &= ~IRQ_DONE;
         // De-flipping the sequence bit.
         if(!(pPacketPointer->flags & RETRANSMISSION))
         {
            pPacketPointer->flags ^= SEQUENCE_BIT;
         }
      }
#endif
   }
   return res;
} // ends sppSend
Example #7
-1
/******************************************************************************
* @fn  writeFlashUsingDMA
*
* @brief
*      Writes data to flash using DMA. Erases the page in advance if told to.
*
* Parameters:
*
* @param  BYTE* pSrcAddr
*         The start of the data to be written to flash.
*
*         INT16 length
*         The number of bytes to be written to flash.
*
*         WORD flashAddress
*         The address in flash the data is to be written to.
*
*         BOOL erase
*         Indicating whether the flash is to be erased or not.
*
* @return void
*
******************************************************************************/
void writeFlashUsingDMA(BYTE* pSrcAddr, INT16 length, WORD flashAddress, BOOL erase)
{
   BYTE buffer[10];

   INT_GLOBAL_ENABLE(INT_OFF);


   // Setting up the flash address,
   // erasing the page if required.
   SET_WORD(FADDRH, FADDRL, (int)(flashAddress >> 1));
   if(erase == TRUE)
   {
      halFlashErasePage(buffer, PAGE_NUMBER);
   }

   halWait(0xFF);

   // Making sure a multiplum of 4 bytes is transferred.
   while(length & 0x0003){
      length++;
   }


   SET_WORD(dmaChannel.SRCADDRH, dmaChannel.SRCADDRL,   pSrcAddr);   // The start address of the segment
   SET_WORD(dmaChannel.DESTADDRH, dmaChannel.DESTADDRL, &X_FWDATA);  // Input of the AES module
   SET_WORD(dmaChannel.LENH, dmaChannel.LENL, length);               // Setting the length of the transfer (bytes)
   dmaChannel.VLEN      = VLEN_USE_LEN;      // Using the length field
   dmaChannel.PRIORITY  = PRI_LOW;          // High priority
   dmaChannel.M8        = M8_USE_8_BITS;     // Transferring all 8 bits in each byte.
   dmaChannel.IRQMASK   = FALSE;             // The DMA complete interrupt flag is set at completion.
   dmaChannel.DESTINC   = DESTINC_0;         // The destination address is constant
   dmaChannel.SRCINC    = SRCINC_1;          // The address for data fetch is inremented by 1 byte
   dmaChannel.TRIG      = DMATRIG_FLASH;     // Setting the FLASH module to generate the DMA trigger
   dmaChannel.TMODE     = TMODE_SINGLE;      // A single byte is transferred each time.
   dmaChannel.WORDSIZE  = WORDSIZE_BYTE;     // Set to count bytes.

   // Setting up the DMA.
   // Clearing all DMA complete flags and arming the channel.
   DMA_SET_ADDR_DESC0(&dmaChannel);
   DMA_ABORT_CHANNEL(0);
   DMAIRQ &= ~DMA_CHANNEL_0;
   DMA_ARM_CHANNEL(0);

   asm("NOP");

   // Starting to write
   FLASH_CONFIG(WRITE);

   // Waiting for the DMA to finish.
   while(!(DMAIRQ & DMA_CHANNEL_0));
   DMAIRQ &= ~DMA_CHANNEL_0;

   return;
}