/*
* FUNCTION
* GPT_ResetTimer
*
* DESCRIPTION
* This function is to setup GPT parameters
*
* CALLS
* It is called to setup GPT parameters
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
* countValue = GPT count
* autoReload = KAL_TRUE,autoReload mode
* KAL_FALSE, Single shot mode
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_ResetTimer(kal_uint8 timerNum,kal_uint16 countValue,kal_bool autoReload)
{
if (timerNum == 1)
{
DRV_WriteReg(GPT1_LEN,countValue);
if (autoReload == KAL_TRUE)
{
DRV_Reg(GPT1_CTRL) |= GPT_CTRL_AUTOMODE;
}
else
{
DRV_Reg(GPT1_CTRL) &= ~GPT_CTRL_AUTOMODE;
}
}
if (timerNum == 2)
{
DRV_WriteReg(GPT2_LEN,countValue);
if (autoReload == KAL_TRUE)
{
DRV_Reg(GPT2_CTRL) |= GPT_CTRL_AUTOMODE;
}
else
{
DRV_Reg(GPT2_CTRL) &= ~GPT_CTRL_AUTOMODE;
}
}
}
void PWM2_Configure(kal_uint32 freq, kal_uint8 duty)
{
kal_uint32 clock;
kal_uint32 tmp;
kal_uint16 clkdiv;
kal_uint16 reg;
ASSERT(duty <= 100);
PWM2_FRE_SAVE=freq;
PWM2_DUTY_SAVE=duty;
reg = DRV_Reg(PWM2_CTRL);
clkdiv = (1 << (reg & 0x0003));
if (reg & 0x0004)
clock = 32000;
else
clock = 13000000;
clock = clock/clkdiv;
if(0==freq)
tmp = clock/(freq+1);
else
tmp = clock/(freq);
tmp--;
DRV_WriteReg(PWM2_COUNT,(kal_uint16)tmp);
tmp = ((tmp+1)*duty)/100;
DRV_WriteReg(PWM2_THRESHOLD,(kal_uint16)tmp);
}
static void mtk_wdt_reset(char mode)
{
/* Watchdog Rest */
unsigned short wdt_mode_val;
DRV_WriteReg16(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
wdt_mode_val = DRV_Reg(MTK_WDT_MODE);
/* clear autorestart bit: autoretart: 1, bypass power key, 0: not bypass power key */
wdt_mode_val &=(~MTK_WDT_MODE_AUTO_RESTART);
/* make sure WDT mode is hw reboot mode, can not config isr mode */
wdt_mode_val &=(~(MTK_WDT_MODE_IRQ|MTK_WDT_MODE_ENABLE));
if(mode){ /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART);
//DRV_WriteReg(MTK_WDT_MODE, wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART));
}else{
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN);
//DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN));
}
DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_LENGTH, MTK_WDT_LENGTH_KEY);
gpt_busy_wait_us(100);
DRV_WriteReg(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
}
static void tv_power_on(void)
{
kal_uint32 save_irq_mask;
/// Turn off TV PLL clock
#if defined(DRV_TVOUT_6228_SERIES)
DRV_Reg(DRVPDN_CON0_CLR) = DRVPDN_CON0_TPLL;
#elif defined(DRV_TVOUT_6238_SERIES)
//KKKKK
DRV_WriteReg(TPLL,0xe0);
DRV_WriteReg(TPLL2,0x0);
#endif
/// Power on TV module
DRV_Reg(DRVPDN_CON3_CLR) = DRVPDN_CON3_TV;
save_irq_mask=SaveAndSetIRQMask();
UPLL_Enable(UPLL_OWNER_TV);
RestoreIRQMask(save_irq_mask);
tv_operation_state=TV_DETECTION_STATE;
/* turn on TV DAC */
ENABLE_TV_HALF_BIAS_POWER;
ENABLE_TV_DAC2_POWER;
ENABLE_TV_DAC1_POWER;
ENABLE_TV_DAC0_POWER;
ENABLE_TV_BGVREF_POWER;
ENABLE_TV_DAC_POWER;
ENABLE_TV_ENCODER;
} /* tv_power_on() */
/*
* FUNCTION
* GPTI_BusyWait
*
* DESCRIPTION
* Use GPT2 as a counter to perform a busy waiting
*
* CALLS
*
* PARAMETERS
* len: length of the counter in unit of 1ms
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*/
void GPTI_BusyWait(kal_uint16 len)
{
// disable PDN
#if defined(DRV_MISC_PDN_NO_SET_CLR)
DRV_Reg(DRVPDN_CON1) &= ~DRVPDN_CON1_GPT;
#else
DRV_WriteReg(DRVPDN_CON1_CLR, DRVPDN_CON1_GPT);
#endif
DRV_WriteReg(GPT2_LEN, len);
DRV_WriteReg(GPT2_PRESCALER, clk_1k); // 1K HZ
// one shot
DRV_WriteReg(GPT2_CTRL, GPT_CTRL_Enable);
while(!(DRV_Reg(GPT_STS) & GPT_STS_2));
// set PDN
#if defined(DRV_MISC_PDN_NO_SET_CLR)
DRV_Reg(DRVPDN_CON1) |= DRVPDN_CON1_GPT;
#else
DRV_WriteReg(DRVPDN_CON1_SET, DRVPDN_CON1_GPT);
#endif
}
void MT6573_sw_watchdog_reset(void)
{
/* Watchdog Rest */
DRV_WriteReg16(MT6573_WDT_RESTART, MT6573_WDT_RESTART_KEY);
DRV_WriteReg(MT6573_WDT_MODE, (MT6573_WDT_MODE_KEY|MT6573_WDT_MODE_EXTEN|MT6573_WDT_MODE_ENABLE));
//DRV_WriteReg(MT6573_WDT_LENGTH, MT6573_WDT_LENGTH_KEY);
DRV_WriteReg(MT6573_WDT_SWRST, MT6573_WDT_SWRST_KEY);
}
void B2PSI_write_fast(kal_uint8 data, kal_uint16 register_index)
{
#ifdef __USB_DOWNLOAD__
kal_uint16 write_data=0;
kal_uint16 i, status=0;
// extern kal_uint8 pmic_reg_save[];
#if defined(__DRV_B2SPI_SHARE_PIN__)
b2spi_serial_lock();
B2PSI_init_sharePin();
#endif
write_data=(register_index|B2PSI_WRITE_MASK|data);
DRV_WriteReg(DRVPDN_CON1+0x20,(kal_uint16)DRVPDN_CON1_B2SPI);
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(0, B2PSI_CS_PIN);
for(debug_loop=0;debug_loop<debug_loop_cnt;debug_loop++){};
#endif
//L1D_MeasureMaxDuration_Start( &b2psi_duration );
DRV_WriteReg(B2PSI_DATA,B2PSI_DATA_KEY);
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(1, B2PSI_CS_PIN);
#endif
/*this short loop is becasue B2PSI needs this to change his state machine*/
for(i=0;i<B2SPI_WAIT_CNT;i++){}
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(0, B2PSI_CS_PIN);
for(debug_loop=0;debug_loop<debug_loop_cnt;debug_loop++){};
#endif
DRV_WriteReg(B2PSI_DATA,write_data);
//L1D_MeasureMaxDuration_Stop( &b2psi_duration );
/*write data to reg_save*/
//pmic_reg_save[(register_index>>PMIC_SHIFT_BITS)]=data;
//dbg_data=data;
//dbg_index=register_index;
do
{
status=DRV_Reg(B2PSI_STAT);
}
while(!(status&=0x2));
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(1, B2PSI_CS_PIN);
#endif
#if defined(__DRV_B2SPI_SHARE_PIN__)
serial_init_sharePin();
b2spi_serial_unlock();
#endif
DRV_WriteReg(DRVPDN_CON1+0x10,(kal_uint16)DRVPDN_CON1_B2SPI);
#endif /* __USB_DOWNLOAD__ */
}
/*
* FUNCTION
* GPIO_PullenSetup
*
* DESCRIPTION
* This function is to enable or disable the pull up/down of the related GPIO pin.
* You can not decide to pull up or down, it is set inside the chip.
* And, the setting is different from pin by pin.
*
* PARAMETERS
* enable: enable the pull up/down
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*/
void GPIO_PullenSetup(kal_uint16 pin, kal_bool enable)
{
kal_uint16 modeno;
kal_uint16 remainder;
modeno = pin/16;
remainder = pin % 16;
if(enable)
DRV_WriteReg(GPIO_PULLEN_SET(modeno), 1 << remainder);
else
DRV_WriteReg(GPIO_PULLEN_CLR(modeno), 1 << remainder);
}
/*
* FUNCTION
* IMGPROC_SetBrightContrast
*
* DESCRIPTION
* Set the parameters for brightness and contrast
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
kal_int32 API IMGPROC_SetBrightContrast(MMDI_SCENERIO_ID owner, IMGPROC_BRI_CON_STURCT* s)
{
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(owner == imgproc_dcb.owner);
#elif (defined(DRV_IDP_6228_SERIES))
if (current_image_data_path_owner!=owner)
ASSERT(0);
#endif
DRV_WriteReg(IMGPROC_BRIADJ1,s->bright);
DRV_WriteReg(IMGPROC_BRIADJ2,s->dark);
DRV_WriteReg(IMGPROC_CONADJ,s->contrast);
return NO_ERROR;
}
/*
* FUNCTION
* IMGPROC_SetHUE
*
* DESCRIPTION
* set the parameters for HUE adjustment
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
kal_int32 API IMGPROC_SetHUE(MMDI_SCENERIO_ID owner, IMGPROC_HUE_STURCT* s)
{
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(owner == imgproc_dcb.owner);
#elif (defined(DRV_IDP_6228_SERIES))
if (current_image_data_path_owner!=owner)
ASSERT(0);
#endif
DRV_WriteReg(IMGPROC_HUE11,s->c11);
DRV_WriteReg(IMGPROC_HUE12,s->c12);
DRV_WriteReg(IMGPROC_HUE21,s->c21);
DRV_WriteReg(IMGPROC_HUE22,s->c22);
return NO_ERROR;
}
static void tv_power_off(void)
{
kal_uint32 save_irq_mask;
/* turn off TV DAC */
DISABLE_TV_HALF_BIAS_POWER;
DISABLE_TV_DAC2_POWER;
DISABLE_TV_DAC1_POWER;
DISABLE_TV_DAC0_POWER;
DISABLE_TV_BGVREF_POWER;
DISABLE_TV_DAC_POWER;
DISABLE_TV_ENCODER;
DISABLE_TV_CONTROLLER;
RESET_TV_CONTROLLER;
tv_src_width=0;
tv_src_height=0;
/// Turn off TV PLL clock
#if defined(DRV_TVOUT_6228_SERIES)
DRV_Reg(DRVPDN_CON0_SET) = DRVPDN_CON0_TPLL;
#elif defined(DRV_TVOUT_6238_SERIES)
//KKKKK
DRV_WriteReg(TPLL2,0x1);
#endif
/// Power off TV module
DRV_Reg(DRVPDN_CON3_SET) = DRVPDN_CON3_TV;
save_irq_mask=SaveAndSetIRQMask();
UPLL_Disable(UPLL_OWNER_TV);
RestoreIRQMask(save_irq_mask);
tv_operation_state=TV_IDLE_STATE;
} /* tv_power_off() */
/**********************************************************
Description : Wait for 32KHz clock srouce stable.
Input : None
Output : None
***********************************************************/
void WaitFor32KStable(void)
{
kal_uint32 result;
kal_uint16 result_low;
kal_uint16 result_high;
* (volatile kal_uint16 *) DRVPDN_CON2_CLR = DRVPDN_CON2_TDMA;
DRV_WriteReg(SM_FMDURATION,0);
while(1)
{
DRV_Reg(SM_CTRL) |= SM_CTRL_FM_START;
while(!(DRV_Reg(SM_STAT) & SM_STAT_FM_RDY));
result_low = DRV_Reg(SM_FM_RESULT_LOW);
result_high = DRV_Reg(SM_FM_RESULT_HIGH) & SM_FM_RESULT_HIGH_MASK;
result = (result_low | (result_high << 16));
if ((result < 950) && (result > 650))
break;
}
* (volatile kal_uint16 *) DRVPDN_CON2_SET = DRVPDN_CON2_TDMA;
}
void irda_switch_to_mir(void)
{
/*Vishay 6614*/
#if defined(__IRDA_VISHAY_6102__)
GPIO_WriteIO(1, IRDA_GPIO_MODE_SWITCH);
#elif defined(__IRDA_VISHAY_6614__)
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x1);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x7);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x6);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x4);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x0);
#endif
}
/*
* FUNCTION
* GPT_Stop
*
* DESCRIPTION
* Stop GPT timer
*
* CALLS
* It is called to stop GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Stop(kal_uint8 timerNum)
{
kal_uint16 gpt_ctrl1;
kal_uint16 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
kal_uint16 gpt_ctrl3;
#endif
gpt_ctrl1 = DRV_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_Reg(GPT3_CTRL);
#endif
if (timerNum == 1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
if (timerNum == 2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_WriteReg(GPT3_CTRL,gpt_ctrl3);
}
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)&& (!(gpt_ctrl3&GPT3_ENABLE)))
#else
if ( ((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0 )
#endif
{
kal_uint16 GPT_Status;
GPT_Status = DRV_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
#ifdef GPT_DRVPDN_FAST
DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
}
}
static void mtk_wdt_disable(void)
{
u16 tmp;
tmp = DRV_Reg(MTK_WDT_MODE);
tmp &= ~MTK_WDT_MODE_ENABLE; /* disable watchdog */
tmp |= (MTK_WDT_MODE_KEY); /* need key then write is allowed */
DRV_WriteReg(MTK_WDT_MODE,tmp);
}
void irda_switch_to_fir(void)
{
#if defined(__IRDA_VISHAY_6102__)
/*Vishay 6614*/
GPIO_WriteIO(1, IRDA_GPIO_MODE_SWITCH);
/*Vishay 6102, Anilent 3220*/
#elif defined(__IRDA_AGILENT_3220__)||defined(__IRDA_VISHAY_6614__)
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x1);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x7);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x6);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x4);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x0);
#endif
}
void DRV_PDN_DIS(void *parameter)
{
PDN_INPUT *pdn_data = (PDN_INPUT *)parameter;
#if defined(MT6208) || defined(MT6205)
DRV_Reg(pdn_data->addr) |= pdn_data->code;
#else
DRV_WriteReg((pdn_data->addr+0x20), pdn_data->code);
#endif
}
/* config SRAM back from L2 cache for DA relocation */
void config_shared_SRAM_size(void)
{
volatile unsigned int cache_cfg;
/* set L2C size to 256KB */
cache_cfg = DRV_Reg(MCUSYS_CFGREG_BASE);
cache_cfg &= (~0x7) << L2C_SIZE_CFG_OFF;
cache_cfg |= 0x1 << L2C_SIZE_CFG_OFF;
DRV_WriteReg(MCUSYS_CFGREG_BASE, cache_cfg);
}
void hw_watchdog_disable(void)
{
u16 tmp;
tmp = DRV_Reg(MT6573_WDT_MODE);
tmp &= ~MT6573_WDT_MODE_ENABLE; /* disable watchdog */
tmp |= (MT6573_WDT_MODE_KEY); /* need key then write is allowed */
DRV_WriteReg(MT6573_WDT_MODE,tmp);
}
/*conf_data = 0~3*/
void GPIO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 modeno;
kal_uint16 remainder;
modeno = pin/8;
remainder = pin % 8;
#if defined(MT6226)|| defined(MT6227)
if(pin>=56)/*special case */
{
DRV_WriteReg(GPIO_MODE8_CLR,(0x0003 << (remainder*2)));
DRV_WriteReg(GPIO_MODE8_SET,(conf_dada << (remainder*2)));
return;
}
#endif
DRV_WriteReg(GPIO_MODE_CLR(modeno),(0x0003 << (remainder*2)));
DRV_WriteReg(GPIO_MODE_SET(modeno),(conf_dada << (remainder*2)));
}
/*conf_data = 0~3*/
void GPO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 mode;
mode = DRV_Reg(GPI_O_MODE);
mode &= ~(0x0003 << (pin*2));
mode |= (conf_dada << (pin*2));
DRV_WriteReg(GPI_O_MODE,mode);
}
static void mtk_wdt_reset(char mode)
{
/* Watchdog Rest */
unsigned short wdt_mode_val;
DRV_WriteReg16(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
wdt_mode_val = DRV_Reg(MTK_WDT_MODE);
if(mode){ /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART);
DRV_WriteReg(MTK_WDT_MODE, wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART));
}else{
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN);
DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN));
}
//DRV_WriteReg(MTK_WDT_LENGTH, MTK_WDT_LENGTH_KEY);
gpt_busy_wait_us(100);
DRV_WriteReg(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
}
/*
* FUNCTION
* IMGPROC_SetSAT
*
* DESCRIPTION
* set the saturations
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
kal_int32 API IMGPROC_SetSAT(MMDI_SCENERIO_ID owner, kal_uint8 sat)
{
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(owner == imgproc_dcb.owner);
#elif (defined(DRV_IDP_6228_SERIES))
if (current_image_data_path_owner!=owner)
ASSERT(0);
#endif
DRV_WriteReg(IMGPROC_SAT,sat);
return NO_ERROR;
}
void irda_switch_to_sir(void)
{
#if defined(__IRDA_VISHAY_6102__)
/*Vishay 6614*/
#ifndef __CUST_NEW__
GPIO_ModeSetup(IRDA_GPIO_MODE_SWITCH, 0);
GPIO_InitIO(OUTPUT, IRDA_GPIO_MODE_SWITCH);
#endif /* __CUST_NEW__ */
GPIO_WriteIO(0, IRDA_GPIO_MODE_SWITCH);
#elif defined(__IRDA_AGILENT_3220__)||defined(__IRDA_VISHAY_6614__)
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x1);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x5);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x4);
irda_delay(irda_test_delay);
DRV_WriteReg(IR_TRANSCEIVER_PDN,0x0);
#endif
}
/*conf_data = 0~3*/
void GPO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 mode;
kal_uint32 savedMask;
savedMask = SAVEANDSETIRQMASK();
mode = DRV_Reg(GPIO_MODE4);
mode &= ~(0x0003 << (pin*2));
mode |= (conf_dada << (pin*2));
DRV_WriteReg(GPIO_MODE4,mode);
RESTOREIRQMASK(savedMask);
}
/*
* FUNCTION
* GPT_clock
*
* DESCRIPTION
* This function is to setup GPT clock
*
* CALLS
* It is called to setup GPT clock
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
* clock = clk_16k,
* clk_8k,
* clk_4k,
* clk_2k,
* clk_1k,
* clk_500,
* clk_250,
* clk_125
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_clock(kal_uint8 timerNum ,gpt_clock clock)
{
kal_uint16 *ptr_addr=0;
if ( timerNum == 1)
{
ptr_addr = (kal_uint16 *)GPT1_PRESCALER;
}
if ( timerNum == 2)
{
ptr_addr = (kal_uint16 *)GPT2_PRESCALER;
}
switch(clock)
{
case clk_16k:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div2);
break;
case clk_8k:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div4);
break;
case clk_4k:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div8);
break;
case clk_2k:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div16);
break;
case clk_1k:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div32);
break;
case clk_500:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div64);
break;
case clk_250:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div128);
break;
case clk_125:
DRV_WriteReg(ptr_addr,GPT_PRESCALER_div256);
break;
default:
break;
}
}
/*conf_data = 0~3*/
void GPIO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 modeno;
kal_uint16 remainder;
kal_uint16 data;
modeno = pin/8;
remainder = pin % 8;
data=DRV_Reg(GPIO_MODE(modeno));
data&=~(0x3 << (2*remainder));
data|= (conf_dada << (remainder*2));
DRV_WriteReg(GPIO_MODE(modeno),data);
}
/*
* FUNCTION
* IMGPROC_SetMask
*
* DESCRIPTION
* Set the content of the mask(for filtering mode)
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
kal_int32 API IMGPROC_SetMaskContent(MMDI_SCENERIO_ID owner, IMGPROC_MASK_STURCT* s)
{
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(owner == imgproc_dcb.owner);
#elif (defined(DRV_IDP_6228_SERIES))
if (current_image_data_path_owner!=owner)
ASSERT(0);
#endif
DRV_WriteReg(IMGPROC_MASK11,s->c11);
DRV_WriteReg(IMGPROC_MASK12,s->c12);
DRV_WriteReg(IMGPROC_MASK13,s->c13);
DRV_WriteReg(IMGPROC_MASK21,s->c21);
DRV_WriteReg(IMGPROC_MASK22,s->c22);
DRV_WriteReg(IMGPROC_MASK23,s->c23);
DRV_WriteReg(IMGPROC_MASK31,s->c31);
DRV_WriteReg(IMGPROC_MASK32,s->c32);
DRV_WriteReg(IMGPROC_MASK33,s->c33);
return NO_ERROR;
}
/*
* FUNCTION
* GCU_InputData
*
* DESCRIPTION
* Input GPRS Encryption Algorithm keys.
* (Message keys and Secret keys)
*
* CALLS
*
* PARAMETERS
* data: the struct of the message keys and secret keys
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GCU_InputData(gcu_input *data)
{
//Secret Key 0-4
DRV_WriteReg(GCU_KC0,data->SK0);
DRV_WriteReg(GCU_KC1,data->SK1);
DRV_WriteReg(GCU_KC2,data->SK2);
DRV_WriteReg(GCU_KC3,data->SK3);
//Message Key 0-1
DRV_WriteReg(GCU_INPUT0,data->MK0);
DRV_WriteReg(GCU_INPUT1,data->MK1);
if (data->DIRECTION == 1)
DRV_WriteReg(GCU_CTRL,(GCU_CTRL_DIR |GCU_CTRL_NORMAL));
else
DRV_WriteReg(GCU_CTRL,GCU_CTRL_NORMAL);
}
/*conf_data = 0~3*/
void GPIO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 modeno;
kal_uint16 remainder;
kal_uint16 data;
kal_uint32 savedMask;
modeno = pin/8;
remainder = pin % 8;
savedMask = SAVEANDSETIRQMASK();
data=DRV_Reg(GPIO_MODE(modeno));
data&=~(0x3 << (2*remainder));
data|= (conf_dada << (remainder*2));
DRV_WriteReg(GPIO_MODE(modeno),data);
RESTOREIRQMASK(savedMask);
}