/*FUNCTION*-------------------------------------------------------------------
*
* Function Name : ftfl_ram_function
* Returned Value : void
* Comments :
* Code required to run in SRAM to perform flash commands.
* All else can be run in flash.
* Parameter is an address of flash status register and function to invalidate cache.
*
*END*-----------------------------------------------------------------------*/
static void ftfl_ram_function
(
/* [IN] Flash info structure */
volatile uint8_t *ftfl_fstat_ptr,
/* [IN] Pointer to function of invalidate cache*/
void (* invalidate_cache)(volatile uint32_t)
)
{
/* start flash write */
*ftfl_fstat_ptr |= FTFL_FSTAT_CCIF_MASK;
/* wait until execution complete */
while (0 == ((*ftfl_fstat_ptr) & FTFL_FSTAT_CCIF_MASK))
{ /* void */ }
if(invalidate_cache != NULL)
{
invalidate_cache((uint32_t)FLASHX_INVALIDATE_CACHE_ALL);
}
/* Flush the pipeline and ensures that all previous instructions are completed
* before executing new instructions in flash */
#ifdef ISB
ISB();
#endif
#ifdef DSB
DSB();
#endif
}
/**
* @brief Architectural dependant idle loop
*
* WFI instruction is used to put system into sleep.
* We do not use deep sleep since SYSTICK will stop in this
* mode. See InterruptInit () for initialization.
*/
void
IdleLoop ()
{
#ifdef __IDLE_WFI__
DSB ();
while (1) __asm__ volatile ("wfi\n\t");
#else
while (1);
#endif
}
/**
* \brief Disable RX & reset registers and descriptor list
* \param gmacd Pointer to GMAC Driver instance.
*/
static void _gmacd_reset_rx(struct _gmacd* gmacd, uint8_t queue)
{
struct _gmacd_queue* q = &gmacd->queues[queue];
uint32_t addr = (uint32_t)q->rx_buffer;
uint32_t i;
/* Disable RX */
gmac_receive_enable(gmacd->gmac, false);
/* Setup the RX descriptors */
q->rx_head = 0;
for (i = 0; i < q->rx_size; i++) {
q->rx_desc[i].addr = addr & GMAC_RX_ADDR_MASK;
DSB();
q->rx_desc[i].status = 0;
addr += GMAC_RX_UNITSIZE;
}
q->rx_desc[q->rx_size - 1].addr |= GMAC_RX_ADDR_WRAP;
/* Receive Buffer Queue Pointer Register */
gmac_set_rx_desc(gmacd->gmac, queue, q->rx_desc);
}
/**
* \brief Disable TX & reset registers and descriptor list
* \param gmacd Pointer to GMAC Driver instance.
*/
static void _gmacd_reset_tx(struct _gmacd* gmacd, uint8_t queue)
{
struct _gmacd_queue* q = &gmacd->queues[queue];
uint32_t addr = (uint32_t)q->tx_buffer;
uint32_t i;
/* Disable TX */
gmac_transmit_enable(gmacd->gmac, false);
/* Setup the TX descriptors */
RING_CLEAR(q->tx_head, q->tx_tail);
for (i = 0; i < q->tx_size; i++) {
q->tx_desc[i].addr = addr;
DSB();
q->tx_desc[i].status = GMAC_TX_STATUS_USED;
addr += GMAC_TX_UNITSIZE;
}
q->tx_desc[q->tx_size - 1].status |= GMAC_TX_STATUS_WRAP;
/* Transmit Buffer Queue Pointer Register */
gmac_set_tx_desc(gmacd->gmac, queue, q->tx_desc);
}
/* basic system set up (performed during reset, and Disk Boot) */
EXPORT void resetSystem(W boot)
{
MEMSEG *mp;
UW i, va;
printk("%s\n", __func__);
return ;
/* obtain DipSw status */
if (!boot) DipSw = DipSwStatus();
DisCacheMMU();
/* set up interrupt controller */
out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
out_w(IT0_IDS1, ~0);
out_w(IT0_IDS2, ~0);
out_w(IT0_IIR, ~0);
out_w(IT3_IPI0_CLR, 0x0000003f);
out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
out_w(IT3_IDS1, ~0);
out_w(IT3_IDS2, ~0);
out_w(IT3_IIR, ~0);
out_w(IT0_IPI3_CLR, 0x0000003f);
out_w(IT0_FID, 0x00000001); /* CPU: FIQ disabled */
out_w(GIO_IIA(GIO_L), 0); /* GPIO: interrupt disabled */
out_w(GIO_IIA(GIO_H), 0);
out_w(GIO_IIA(GIO_HH), 0);
out_w(GIO_IIA(GIO_HHH), 0);
out_w(GIO_GSW(GIO_L), 0); /* GPIO: FIQ interrupt disabled */
out_w(GIO_GSW(GIO_H), 0);
out_w(GIO_GSW(GIO_HH), 0);
out_w(GIO_GSW(GIO_HHH), 0);
out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
out_w(IT_PINV_CLR0, ~0); /* inhibit interrupt polarity inversion */
out_w(IT_PINV_CLR1, ~0);
out_w(IT_PINV_CLR2, ~0);
out_w(IT0_IEN0, 0x0c000000); /* CPU: GPIO interrupt enabled */
out_w(IT0_IEN1, 0x003c0000);
out_w(IT0_IEN2, 0x00018000);
/* power on controller initialization */
pmicInit();
/* USB power on */
usbPower(TRUE);
/* clear system common area (vector table, and SysInfo) */
memset(&SCInfo, 0, sizeof(SysCommonInfo));
memset(SCArea, 0, sizeof(SysCommonArea));
/* if monitor is loaded into RAM, exclude the RAM area */
mp = MemArea(MSA_OS, 1);
va = (UW)&__loadaddr;
if (va >= mp->top && va < mp->end) mp->end = va;
/* exclude the area where ROM disk data is stored */
va = (UW)ROMInfo->userarea;
if (va >= mp->top && va < mp->end) mp->end = va;
/* initialize system common information (SysInfo) */
SCInfo.ramtop = (void*)mp->top;
if (va < mp->top || va > mp->end) va = mp->end;
SCInfo.ramend = (void*)va;
/* set up EIT vectors */
/* we do not need _defaultHdr absolutely, but just in case set it up */
SCArea->intvec[EIT_DEFAULT] = _defaultHdr; /* default handler */
SCArea->intvec[EIT_UNDEF] = _defaultHdr; /* undefined instruction */
SCArea->intvec[SWI_MONITOR] = _defaultHdr; /* SWI - monitor SVC */
SCArea->intvec[EIT_IRQ(26)] = _gio6Hdr; /* GPIO branch */
SCArea->intvec[EIT_IRQ(27)] = _gio7Hdr;
SCArea->intvec[EIT_IRQ(50)] = _gio0Hdr;
SCArea->intvec[EIT_IRQ(51)] = _gio1Hdr;
SCArea->intvec[EIT_IRQ(52)] = _gio2Hdr;
SCArea->intvec[EIT_IRQ(53)] = _gio3Hdr;
SCArea->intvec[EIT_IRQ(79)] = _gio4Hdr;
SCArea->intvec[EIT_IRQ(80)] = _gio5Hdr;
SCArea->intvec[EIT_IRQ(8)] = _defaultHdr; /* abort switch */
/* set up initial page table */
for (i = 0; i < N_MemSeg; ++i) {
mp = &MemSeg[i];
if (!mp->pa) continue;
/* FlashROM has already been mapped, and so do not touch it */
if (mp->attr == MSA_FROM) continue;
/* set up in unit of section (1MB) */
for ( va = (mp->top & 0xfff00000);
va != ((mp->end + 0x000fffff) & 0xfff00000);
va += 0x00100000 ) {
TopPageTable[va / 0x00100000] =
((mp->pa & 0xfff00000) + va) |
(mp->pa & 0x000fffff);
}
}
for (i = 0; i < N_NoMemSeg; ++i) {
mp = &NoMemSeg[i];
/* set up in unit of section (1MB) */
for ( va = (mp->top & 0xfff00000);
va != ((mp->end + 0x000fffff) & 0xfff00000);
va += 0x00100000 ) {
TopPageTable[va / 0x00100000] = 0;
}
}
DSB();
Asm("mcr p15, 0, %0, cr8, c7, 0":: "r"(0)); /* I/D TLB invalidate */
Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0)); /* invalidate BTC */
DSB();
ISB();
EnbCacheMMU();
return;
}
int main(int argc, char* argv[])
{
#if 0
std::cout << "size adapter::Device : " << sizeof(adapter::Device) << std::endl;
std::cout << "size adapter::Method : " << sizeof(adapter::Method) << std::endl;
std::cout << "size adapter::Prop : " << sizeof(adapter::Property) << std::endl;
std::cout << "size adpater::Intf : " << sizeof(adapter::Interface) << std::endl;
std::cout << "size std::string : " << sizeof(std::string) << std::endl;
std::cout << "size adapter::Guid : " << sizeof(adapter::Guid) << std::endl;
std::cout << "size string map<> : " << sizeof(std::map<std::string, std::string>) << std::endl;
#endif
int optionIndex = 0;
char const* adapterName = nullptr;
char const* configFile = "alljoyndsb.xml";
while (true)
{
int c = getopt_long(argc, argv, "a:c:", longOptions, &optionIndex);
if (c == -1)
break;
switch (c)
{
case 'a':
adapterName = optarg;
break;
case 'c':
configFile = optarg;
break;
default:
return 0;
}
}
#if 0
bridge::bridgeConfig config;
config.FromFile("/some/file.xml");
std::cout << config.GetBridgeKeyX() << std::endl;
std::cout << config.GetDeviceKeyX() << std::endl;
std::cout << config.GetDeviceUsername() << std::endl;
std::cout << config.GetDevicePassword() << std::endl;
std::cout << config.GetDeviceEcdheEcdsaPrivateKey() << std::endl;
std::cout << config.GetDeviceEcdheEcdsaCertChain() << std::endl;
std::cout << config.GetDefaultVisibility() << std::endl;
bridge::DsbObjectConfig obj;
QStatus st = config.FindObject("/my/bus/object", obj);
obj.SetId("/my/bus/object2");
obj.SetDescription("This is bus object2");
obj.SetIsVisible(true);
config.AddObject(obj);
obj.SetId("/my/bus/object3");
obj.SetDescription("This is bus object3");
obj.SetIsVisible(true);
config.AddObject(obj);
config.ToFile("/tmp/test.xml");
config.FromFile("/tmp/test.xml");
config.RemoveObject("/my/bus/object2");
config.ToFile("/tmp/test2.xml");
#endif
adapter::Log::SetDefaultLevel(adapter::LogLevel::Debug);
if (!adapterName)
{
DSBLOG_ERROR("need --adapter=<adaptername> argument");
exit(1);
}
adapter::Loader loader(adapterName);
if (!loader.bind())
exit(1);
std::shared_ptr<adapter::Adapter> adapter = loader.create();
bridge::Bridge::InitializeSingleton(adapter);
try
{
DSB()->Initialize(configFile);
}
catch (std::exception const& err)
{
DSBLOG_ERROR("failed to initialize dsb. %s", err.what());
exit(1);
}
#if 0
std::shared_ptr<adapter::Adapter> adapter = DSB()->GetAdapter();
adapter::ItemInformation const& info = adapter->GetInfo();
adapter::Device::Vector devices;
std::shared_ptr<adapter::IoRequest> req(new adapter::IoRequest());
adapter->EnumDevices(adapter::EnumDeviceOptions::ForceRefresh, devices, req);
if (req)
{
DSBLOG_INFO("waiting for EnumDevices to complete");
if (!req->Wait(20000))
DSBLOG_INFO("EnumDevices timed out");
else
DSBLOG_INFO("EnumDevices completed");
}
for (auto const& device : devices)
PrintDevice(*adapter, device);
#endif
getchar();
bridge::Bridge::ReleaseSingleton();
return 0;
}
/**
* \brief Send a frame splitted into buffers. If the frame size is larger than transfer buffer size
* error returned. If frame transfer status is monitored, specify callback for each frame.
* \param gmacd Pointer to GMAC Driver instance.
* \param sgl Pointer to a scatter-gather list describing the buffers of the ethernet frame.
* \param fTxCb Pointer to callback function.
*/
uint8_t gmacd_send_sg(struct _gmacd* gmacd, uint8_t queue,
const struct _gmac_sg_list* sgl, gmacd_callback_t callback)
{
Gmac* gmac = gmacd->gmac;
struct _gmacd_queue* q = &gmacd->queues[queue];
struct _gmac_desc* desc;
uint16_t idx, tx_head;
int i;
if (callback && !q->tx_callbacks) {
trace_error("Cannot set send callback, no tx_callbacks "\
"buffer configured for queue %u", queue);
}
/* Check parameter */
if (!sgl->size) {
trace_error("gmacd_send_sg: ethernet frame is empty.\r\n");
return GMACD_PARAM;
}
if (sgl->size >= q->tx_size) {
trace_error("gmacd_send_sg: ethernet frame has too many buffers.\r\n");
return GMACD_PARAM;
}
/* Check available space */
if (RING_SPACE(q->tx_head, q->tx_tail, q->tx_size) < sgl->size) {
trace_error("gmacd_send_sg: not enough free buffers in TX queue.\r\n");
return GMACD_TX_BUSY;
}
/* Tag end of TX queue */
tx_head = fixed_mod(q->tx_head + sgl->size, q->tx_size);
idx = tx_head;
if (q->tx_callbacks)
q->tx_callbacks[idx] = NULL;
desc = &q->tx_desc[idx];
desc->status |= GMAC_TX_STATUS_USED;
/* Update buffer descriptors in reverse order to avoid a race
* condition with hardware.
*/
for (i = sgl->size - 1; i >= 0; i--) {
const struct _gmac_sg *sg = &sgl->entries[i];
uint32_t status;
if (sg->size > GMAC_TX_UNITSIZE) {
trace_error("gmacd_send_sg: buffer size is too big.\r\n");
return GMACD_PARAM;
}
RING_DEC(idx, q->tx_size);
/* Reset TX callback */
if (q->tx_callbacks)
q->tx_callbacks[idx] = NULL;
desc = &q->tx_desc[idx];
/* Copy data into transmittion buffer */
if (sg->buffer && sg->size) {
memcpy((void*)desc->addr, sg->buffer, sg->size);
l2cc_clean_region(desc->addr, desc->addr + sg->size);
}
/* Compute buffer descriptor status word */
status = sg->size & GMAC_RX_STATUS_LENGTH_MASK;
if (i == (sgl->size - 1)) {
status |= GMAC_TX_STATUS_LASTBUF;
if (q->tx_callbacks)
q->tx_callbacks[idx] = callback;
}
if (idx == (q->tx_size - 1)) {
status |= GMAC_TX_STATUS_WRAP;
}
/* Update buffer descriptor status word: clear USED bit */
desc->status = status;
DSB();
}
/* Update TX ring buffer pointers */
q->tx_head = tx_head;
/* Now start to transmit if it is not already done */
gmac_start_transmission(gmac);
return GMACD_OK;
}
