/* * * Function Name: chal_dsi_tx_short * * Description: Configure packet send interface for sending SHORT packet. * o SHORT PACKET Data is read from input PACKET BUFFFER. * */ CHAL_DSI_RES_t chal_dsi_tx_short(CHAL_HANDLE handle, cUInt8 txEng, pCHAL_DSI_TX_CFG txCfg) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 pktc = 0; cUInt32 pkth = 0; cUInt32 dsi_DT = 0; if (txCfg->msgLen > 2) return CHAL_DSI_MSG_SIZE; if (txCfg->isLP) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_MODE, 1); if (txCfg->endWithBta) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_CTRL, CMND_CTRL_CMND_PKTwBTA); else pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_CTRL, CMND_CTRL_CMND_PKT); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_REPEAT, 1); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_TX_TIME, txCfg->vmWhen); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, DISPLAY_NO, DSI_PKT_SRC_CMND_FIFO); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_EN, 1); if (txCfg->start) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_EN, 1); if (txCfg->isTe) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_TE_EN, 1); dsi_DT = ((txCfg->vc & 0x00000003) << 6) | txCfg->dsiCmnd; /* SHORT MSG IS FIXED IN SIZE (always 2 parms) */ if (txCfg->msgLen >= 1) pkth |= (UInt32)txCfg->msg[0]; if (txCfg->msgLen == 2) pkth |= ((UInt32)txCfg->msg[1] << 8); pkth = DSI_REG_FIELD_SET(DSI1_TXPKT1_H, WC_PARAM, pkth); pkth |= dsi_DT; if (txEng) BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT2_H, pkth); else BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT1_H, pkth); if (txEng) BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT2_C, pktc); else BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT1_C, pktc); return CHAL_DSI_OK; }
/* * * Function Name: chal_dsi_set_afe_off * * Description: Power Down PHY AFE (Analog Front End) * */ cVoid chal_dsi_phy_afe_off(CHAL_HANDLE handle) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 afeVal = 0; cUInt32 afeMask = 0; afeMask = DSI1_PHY_AFEC0_PD_MASK | DSI1_PHY_AFEC0_PD_BG_MASK; afeVal = DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, PD, 1) /* Pwr Down AFE */ | DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, PD_BG, 1); /* Pwr Down BG */ DSI_REG_WRITE_MASKED(pDev->baseAddr, DSI1_PHY_AFEC0, afeMask, afeVal); }
//**************************************************************************** // // Function Name: chal_dsi_phy_state // // Description: PHY State Control // Controls Clock & Data Line States // // CLK lane cannot be directed to STOP state. It is normally in stop state // if cont clock is not enabled. // CLK lane will not transition to ULPS if cont clk is enabled. // When ULPS is requested and cont clock was enabled it will be disabled // at same time as ULPS is activated, and re-enabled upon ULPS exit // //**************************************************************************** cVoid chal_dsi_phy_state ( CHAL_HANDLE handle, CHAL_DSI_PHY_STATE_t state ) { CHAL_DSI_HANDLE pDev = (CHAL_DSI_HANDLE) handle; cUInt32 regMask = 0; cUInt32 regVal = 0; regMask = DSI_REG_FIELD_SET( DSI_PHYC, FORCE_TXSTOP_0, 1 ) | DSI_REG_FIELD_SET( DSI_PHYC, TXULPSCLK , 1 ) | DSI_REG_FIELD_SET( DSI_PHYC, TXULPSESC_0 , 1 ) | DSI_REG_FIELD_SET( DSI_PHYC, TX_HSCLK_CONT , 1 ); switch ( state ) { case PHY_TXSTOP: regVal = DSI_REG_FIELD_SET( DSI_PHYC, FORCE_TXSTOP_0, 1 ); break; case PHY_ULPS: regVal = DSI_REG_FIELD_SET( DSI_PHYC, TXULPSCLK , 1 ) | DSI_REG_FIELD_SET( DSI_PHYC, TXULPSESC_0, 1 ); break; case PHY_CORE: default: if ( pDev->clkContinuous ) regVal = DSI_REG_FIELD_SET( DSI_PHYC, TX_HSCLK_CONT , 1 ); else regVal = 0; break; } DSI_REG_WRITE_MASKED( pDev->baseAddr, DSI_PHYC, regMask, regVal ); }
//**************************************************************************** // // Function Name: chal_dsi_set_afe_off // // Description: Power Down PHY AFE (Analog Front End) // //**************************************************************************** cVoid chal_dsi_phy_afe_off ( CHAL_HANDLE handle ) { CHAL_DSI_HANDLE pDev = (CHAL_DSI_HANDLE) handle; cUInt32 afeVal = 0; cUInt32 afeMask = 0; afeMask = DSI_PHY_AFEC_PD_CLANE_MASK | DSI_PHY_AFEC_PD_DLANE0_MASK | DSI_PHY_AFEC_PD_BG_MASK | DSI_PHY_AFEC_PD_MASK; afeVal = DSI_REG_FIELD_SET( DSI_PHY_AFEC, PD , 1 ) // Pwr Down AFE | DSI_REG_FIELD_SET( DSI_PHY_AFEC, PD_CLANE , 1 ) // Pwr Down CL | DSI_REG_FIELD_SET( DSI_PHY_AFEC, PD_DLANE0, 1 ) // Pwr Down DLx | DSI_REG_FIELD_SET( DSI_PHY_AFEC, PD_BG , 1 ); // Pwr Down BG DSI_REG_WRITE_MASKED ( pDev->baseAddr, DSI_PHY_AFEC, afeMask, afeVal ); }
/* * * Function Name: chal_dsi_phy_afe_on * * Description: Configure & Enable PHY-AFE (Analog Front End) * */ cVoid chal_dsi_phy_afe_on(CHAL_HANDLE handle, pCHAL_DSI_AFE_CFG afeCfg) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 afeVal = 0; cUInt32 afeMask = 0; /*cUInt32 i; */ afeMask = DSI1_PHY_AFEC0_CTATADJ_MASK | DSI1_PHY_AFEC0_PTATADJ_MASK | DSI1_PHY_AFEC0_DDRCLK_EN_MASK | DSI1_PHY_AFEC0_PD_BG_MASK | DSI1_PHY_AFEC0_PD_MASK | DSI1_PHY_AFEC0_RESET_MASK | DSI1_PHY_AFEC0_DDR2CLK_EN_MASK | DSI1_PHY_AFEC0_IDR_DLANE0_MASK | DSI1_PHY_AFEC0_IDR_CLANE_MASK; afeVal = DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, CTATADJ, afeCfg->afeCtaAdj) | DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, PTATADJ, afeCfg->afePtaAdj) | DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, IDR_CLANE, afeCfg->afeClkIdr) | DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, IDR_DLANE0, afeCfg->afeDlIdr); /* if( !afeCfg->afeBandGapOn ) */ /* afeVal |= DSI_REG_FIELD_SET( DSI1_PHY_AFEC0, PD_BG, 1 ); */ /* */ /* if( afeCfg->afeDs2xClkEna ) */ /* afeVal |= DSI_REG_FIELD_SET( DSI1_PHY_AFEC0, DDRCLK_EN, 1 ); */ rmb(); afeVal |= DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, PD_BG, 0); afeVal |= DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, PD, 0); /* for now, enable all clock outputs */ afeVal |= DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, DDRCLK_EN, 1); afeVal |= DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, DDR2CLK_EN, 1); afeVal |= DSI_REG_FIELD_SET(DSI1_PHY_AFEC0, RESET, 1); /* PWR-UP & Reset */ wmb(); DSI_REG_WRITE_MASKED(pDev->baseAddr, DSI1_PHY_AFEC0, afeMask, afeVal); /*for ( i=0; i<100; i++ ) {} */ CHAL_DELAY_MS(2); /* remove reset */ wmb(); BRCM_WRITE_REG_FIELD(pDev->baseAddr, DSI1_PHY_AFEC0, RESET, 0); }
//**************************************************************************** // // Function Name: chal_dsi_phy_afe_on // // Description: Configure & Enable PHY-AFE (Analog Front End) // Power Up CLK & DLs //**************************************************************************** cVoid chal_dsi_phy_afe_on ( CHAL_HANDLE handle, pCHAL_DSI_AFE_CFG afeCfg ) { CHAL_DSI_HANDLE pDev = (CHAL_DSI_HANDLE) handle; cUInt32 afeVal = 0; cUInt32 afeMask = 0; cUInt32 i; #if (CHIP_REVISION >= 20) afeMask = DSI_PHY_AFEC_CTATADJ_MASK | DSI_PHY_AFEC_PTATADJ_MASK | DSI_PHY_AFEC_FS2X_EN_CLK_MASK | DSI_PHY_AFEC_RESET_MASK | DSI_PHY_AFEC_PD_CLANE_MASK | DSI_PHY_AFEC_PD_DLANE0_MASK | DSI_PHY_AFEC_PD_BG_MASK | DSI_PHY_AFEC_PD_MASK | DSI_PHY_AFEC_IDR_CLANE_MASK | DSI_PHY_AFEC_IDR_DLANE0_MASK; afeVal = DSI_REG_FIELD_SET( DSI_PHY_AFEC, CTATADJ , afeCfg->afeCtaAdj ) | DSI_REG_FIELD_SET( DSI_PHY_AFEC, PTATADJ , afeCfg->afePtaAdj ) | DSI_REG_FIELD_SET( DSI_PHY_AFEC, IDR_CLANE , afeCfg->afeClkIdr ) | DSI_REG_FIELD_SET( DSI_PHY_AFEC, IDR_DLANE0, afeCfg->afeDlIdr ); #else afeMask = DSI_PHY_AFEC_CTATADJ_MASK | DSI_PHY_AFEC_PTATADJ_MASK | DSI_PHY_AFEC_FS2X_EN_CLK_MASK | DSI_PHY_AFEC_RESET_MASK | DSI_PHY_AFEC_PD_CLANE_MASK | DSI_PHY_AFEC_PD_DLANE0_MASK | DSI_PHY_AFEC_PD_BG_MASK | DSI_PHY_AFEC_PD_MASK; afeVal = DSI_REG_FIELD_SET( DSI_PHY_AFEC, CTATADJ , afeCfg->afeCtaAdj ) | DSI_REG_FIELD_SET( DSI_PHY_AFEC, PTATADJ , afeCfg->afePtaAdj ); #endif if( !afeCfg->afeBandGapOn ) afeVal |= DSI_REG_FIELD_SET( DSI_PHY_AFEC, PD_BG, 1 ); if( afeCfg->afeDs2xClkEna ) afeVal |= DSI_REG_FIELD_SET( DSI_PHY_AFEC, FS2X_EN_CLK, 1 ); afeVal |= DSI_PHY_AFEC_RESET_MASK; // reset AFE + PWR-UP DSI_REG_WRITE_MASKED ( pDev->baseAddr, DSI_PHY_AFEC, afeMask, afeVal ); for ( i=0; i<100; i++ ) {} // remove RESET BRCM_WRITE_REG_FIELD ( pDev->baseAddr, DSI_PHY_AFEC, RESET, 0 ); }
//**************************************************************************** // // Function Name: chal_dsi_send_trig // // Description: Send TRIGGER Message // //**************************************************************************** cVoid chal_dsi_send_trig ( CHAL_HANDLE handle, cUInt8 txEng, // NA to ATHENA cUInt8 trig ) { CHAL_DSI_HANDLE pDev = (CHAL_DSI_HANDLE) handle; cUInt32 pktc = 0; pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_CTRL , CMND_CTRL_TRIG ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_REPEAT , 1 ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_MODE , 1 ); // LowPower pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_TX_TIME, CHAL_DSI_CMND_WHEN_BEST_EFFORT ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, DISPLAY_NO , DSI_PKT_SRC_CMND_FIFO ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_EN , 1 ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, TRIG_CMD , trig ); BRCM_WRITE_REG ( pDev->baseAddr, DSI_CMD_PKTC, pktc ); }
/* * * Function Name: chal_dsi_tx_trig * * Description: Send TRIGGER Message * */ cVoid chal_dsi_tx_trig(CHAL_HANDLE handle, cUInt8 txEng, cUInt8 trig) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 pktc = 0; pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_CTRL, CMND_CTRL_TRIG); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_REPEAT, 1); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_MODE, 1); /* LowPower */ pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_TX_TIME, CHAL_DSI_CMND_WHEN_BEST_EFFORT); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, DISPLAY_NO, DSI_PKT_SRC_CMND_FIFO); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_EN, 1); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, TRIG_CMD, trig); if (txEng) BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT2_C, pktc); else BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT1_C, pktc); }
//**************************************************************************** // // Function Name: chal_dsi_send_cmnd // // Description: Send SHORT CMND - up to 2 Byte Parms - LSB first on wire // | LONG CMND - up to 8 Byte Parms - LSB first on wire // //**************************************************************************** CHAL_DSI_RES_t chal_dsi_send_cmnd ( CHAL_HANDLE handle, cUInt8 txEng, // NA to ATHENA pCHAL_DSI_CMND cmnd ) { CHAL_DSI_HANDLE pDev = (CHAL_DSI_HANDLE) handle; cUInt32 i; cUInt32 pktc = 0; cUInt32 pkth = 0; cUInt32 dsi_DT = 0; if( !cmnd->isLong && cmnd->msgLen > 2 ) return ( CHAL_DSI_MSG_SIZE ); if( cmnd->isLong && cmnd->msgLen > 8 ) return ( CHAL_DSI_MSG_SIZE ); if( cmnd->isLP ) pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_MODE , 1 ); //pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_MODE , 0 ); if( cmnd->isLong ) pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_TYPE , 1 ); if( cmnd->endWithBta ) pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_CTRL, CMND_CTRL_CMND_PKTwBTA ); else pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_CTRL, CMND_CTRL_CMND_PKT ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_REPEAT , 1 ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_TX_TIME, cmnd->vmWhen ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, DISPLAY_NO , DSI_PKT_SRC_CMND_FIFO ); pktc |= DSI_REG_FIELD_SET( DSI_CMD_PKTC, CMD_EN , 1 ); dsi_DT = ((cmnd->vc & 0x00000003) << 6) | cmnd->dsiCmnd; if ( cmnd->isLong ) { // for long, parm byteCount && byteCount from CMND DATA FIFO are same, pkth = DSI_REG_FIELD_SET ( DSI_CMD_PKTH, WC_FIFO, cmnd->msgLen ) | DSI_REG_FIELD_SET ( DSI_CMD_PKTH, WC_PARAM, cmnd->msgLen ); } else { // SHORT MSG IS FIXED IN SIZE (always 2 parms) pkth = cmnd->msg[0]; // if( cmnd->msgLen == 2 ) pkth |= (cmnd->msg[1] << 8); pkth = DSI_REG_FIELD_SET ( DSI_CMD_PKTH, WC_PARAM, pkth ); } pkth |= dsi_DT; BRCM_WRITE_REG ( pDev->baseAddr, DSI_CMD_PKTH, pkth ); // if LONG PKT, fill CMND DATA FIFO if( cmnd->isLong ) { for( i=0; i < cmnd->msgLen; i++ ) { BRCM_WRITE_REG ( pDev->baseAddr, DSI_CMD_DATA_FIFO, cmnd->msg[i] ); } } BRCM_WRITE_REG ( pDev->baseAddr, DSI_CMD_PKTC, pktc ); return ( CHAL_DSI_OK ); }
//**************************************************************************** // // Function Name: chal_dsi_on // // Description: // //**************************************************************************** cVoid chal_dsi_on ( CHAL_HANDLE handle, pCHAL_DSI_MODE dsiMode ) { CHAL_DSI_HANDLE pDev = (CHAL_DSI_HANDLE) handle; cUInt32 mask = 0; cUInt32 ctrl = 0; // DSI_CTRL_CAL_BYTE_EN // DSI_CTRL_INV_BYTE_EN // DSI_CTRL_SOFT_RESET_CFG // DSI_CTRL_DSI_EN // DSI_CTRL_CLR_LANED_FIFO // DSI_CTRL_CLR_PIX_BYTEC_FIFO // DSI_CTRL_CLR_CMD_PIX_BYTEC_FIFO // DSI_CTRL_CLR_PIX_DATA_FIFO // DSI_CTRL_CLR_CMD_DATA_FIFO // DSI-CTRL Configure Modes & enable the core // ------------------------------------------- mask = DSI_REG_FIELD_SET( DSI_CTRL, NO_DISP_CRC , 1 ) | DSI_REG_FIELD_SET( DSI_CTRL, NO_DISP_ECC , 1 ) | DSI_REG_FIELD_SET( DSI_CTRL, RX_LPDT_EOT_EN, 1 ) | DSI_REG_FIELD_SET( DSI_CTRL, LPDT_EOT_EN , 1 ) | DSI_REG_FIELD_SET( DSI_CTRL, HSDT_EOT_EN , 1 ) // | DSI_REG_FIELD_SET( DSI_CTRL, HS_CLKC , 3 ) | DSI_REG_FIELD_SET( DSI_CTRL, DSI_EN , 1 ); if( !dsiMode->enaRxCrc ) ctrl |= DSI_REG_FIELD_SET( DSI_CTRL, NO_DISP_CRC, 1 ); if( !dsiMode->enaRxEcc ) ctrl |= DSI_REG_FIELD_SET( DSI_CTRL, NO_DISP_ECC, 1 ); if( dsiMode->enaHsTxEotPkt ) ctrl |= DSI_REG_FIELD_SET( DSI_CTRL, HSDT_EOT_EN, 1 ); if( dsiMode->enaLpTxEotPkt ) ctrl |= DSI_REG_FIELD_SET( DSI_CTRL, LPDT_EOT_EN, 1 ); if( dsiMode->enaLpRxEotPkt ) ctrl |= DSI_REG_FIELD_SET( DSI_CTRL, RX_LPDT_EOT_EN, 1 ); ctrl |= DSI_REG_FIELD_SET( DSI_CTRL, DSI_EN, 1 ); DSI_REG_WRITE_MASKED ( pDev->baseAddr, DSI_CTRL, mask, ctrl ); // PHY-C Configure & Enable D-PHY Interface // ----------------------------------------- mask = 0; ctrl = 0; // DSI_PHYC_TXULPSCLK // DSI_PHYC_FORCE_TXSTOP_0 // DSI_PHYC_FORCE_TXSTOP_1 // DSI_PHYC_TXULPSESC_0 // DSI_PHYC_TXULPSESC_1 mask = DSI_PHYC_TX_HSCLK_CONT_MASK | DSI_PHYC_PHY_CLANE_EN_MASK | DSI_PHYC_PHY_DLANE0_EN_MASK; if ( dsiMode->enaContClock ) ctrl |= DSI_REG_FIELD_SET( DSI_PHYC, TX_HSCLK_CONT, 1 ); ctrl |= DSI_REG_FIELD_SET( DSI_PHYC, PHY_CLANE_EN , 1 ); ctrl |= DSI_REG_FIELD_SET( DSI_PHYC, PHY_DLANE0_EN, 1 ); DSI_REG_WRITE_MASKED ( pDev->baseAddr, DSI_PHYC, mask, ctrl ); }
/* * * Function Name: chal_dsi_on * * Description: * */ cVoid chal_dsi_on(CHAL_HANDLE handle, pCHAL_DSI_MODE dsiMode) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 mask = 0; cUInt32 ctrl = 0; /* DSI-CTRL Configure Mode & enable the core */ mask = DSI_REG_FIELD_SET(DSI1_CTRL, DISP_CRCC, 1) | DSI_REG_FIELD_SET(DSI1_CTRL, DISP_ECCC, 1) | DSI_REG_FIELD_SET(DSI1_CTRL, RX_LPDT_EOT_EN, 1) | DSI_REG_FIELD_SET(DSI1_CTRL, LPDT_EOT_EN, 1) | DSI_REG_FIELD_SET(DSI1_CTRL, HSDT_EOT_EN, 1) | DSI_REG_FIELD_SET(DSI1_CTRL, DSI_EN, 1) | DSI1_CTRL_HS_CLKC_MASK; ctrl = dsiMode->clkSel << DSI1_CTRL_HS_CLKC_SHIFT; rmb(); if (dsiMode->enaRxCrc) ctrl |= DSI_REG_FIELD_SET(DSI1_CTRL, DISP_CRCC, 1); if (dsiMode->enaRxEcc) ctrl |= DSI_REG_FIELD_SET(DSI1_CTRL, DISP_ECCC, 1); if (dsiMode->enaHsTxEotPkt) ctrl |= DSI_REG_FIELD_SET(DSI1_CTRL, HSDT_EOT_EN, 1); if (dsiMode->enaLpTxEotPkt) ctrl |= DSI_REG_FIELD_SET(DSI1_CTRL, LPDT_EOT_EN, 1); if (dsiMode->enaLpRxEotPkt) ctrl |= DSI_REG_FIELD_SET(DSI1_CTRL, RX_LPDT_EOT_EN, 1); ctrl |= DSI_REG_FIELD_SET(DSI1_CTRL, DSI_EN, 1); wmb(); DSI_REG_WRITE_MASKED(pDev->baseAddr, DSI1_CTRL, mask, ctrl); /* PHY-C Configure & Enable D-PHY Interface */ mask = 0; ctrl = 0; mask = DSI1_PHYC_TX_HSCLK_CONT_MASK | DSI1_PHYC_PHY_CLANE_EN_MASK | DSI1_PHYC_PHY_DLANE0_EN_MASK; rmb(); if (dsiMode->enaContClock) ctrl |= DSI_REG_FIELD_SET(DSI1_PHYC, TX_HSCLK_CONT, 1); ctrl |= DSI_REG_FIELD_SET(DSI1_PHYC, PHY_CLANE_EN, 1); ctrl |= DSI_REG_FIELD_SET(DSI1_PHYC, PHY_DLANE0_EN, 1); wmb(); DSI_REG_WRITE_MASKED(pDev->baseAddr, DSI1_PHYC, mask, ctrl); }
/* * * Function Name: chal_dsi_tx_long * * Description: Configure packet send interface for sending long * packets using CMND or CMND & PIXEL FIFO. * Caller is responsible for handling FIFOs content, input * PACKET BUFFER in not used by the call. * */ CHAL_DSI_RES_t chal_dsi_tx_long(CHAL_HANDLE handle, cUInt8 txEng, pCHAL_DSI_TX_CFG txCfg) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 pktc = 0; cUInt32 pkth = 0; cUInt32 dsi_DT = 0; cUInt32 pfifo_count_b; if (txCfg->msgLenCFifo > CHAL_DSI_CMND_FIFO_SIZE_B) return CHAL_DSI_MSG_SIZE; pfifo_count_b = txCfg->msgLen - txCfg->msgLenCFifo; if ((pfifo_count_b > CHAL_DSI_PIXEL_FIFO_SIZE_B) || (pfifo_count_b % 4 != 0)) { return CHAL_DSI_MSG_SIZE; } if (txCfg->isLP) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_MODE, 1); /* long */ pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_TYPE, 1); if (txCfg->endWithBta) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_CTRL, CMND_CTRL_CMND_PKTwBTA); else pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_CTRL, CMND_CTRL_CMND_PKT); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_REPEAT, txCfg->repeat); pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_TX_TIME, txCfg->vmWhen); if (txCfg->msgLen == txCfg->msgLenCFifo) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, DISPLAY_NO, DSI_PKT_SRC_CMND_FIFO); else pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, DISPLAY_NO, DSI_PKT_SRC_DE1); if (txCfg->isTe) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_TE_EN, 1); if (txCfg->start) pktc |= DSI_REG_FIELD_SET(DSI1_TXPKT1_C, CMD_EN, 1); dsi_DT = ((txCfg->vc & 0x00000003) << 6) | txCfg->dsiCmnd; pkth = DSI_REG_FIELD_SET(DSI1_TXPKT1_H, WC_CDFIFO, txCfg->msgLenCFifo) | DSI_REG_FIELD_SET(DSI1_TXPKT1_H, WC_PARAM, txCfg->msgLen); pkth |= dsi_DT; if (txEng) BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT2_H, pkth); else BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT1_H, pkth); /* chal_dprintf ( CDBG_ERRO, "[cHAL DSI] %s: PKTC[0x%08X] PKTH[0x%08X]\n", */ /* __FUNCTION__, pktc , pktc ); */ if (txEng) BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT2_C, pktc); else BRCM_WRITE_REG(pDev->baseAddr, DSI1_TXPKT1_C, pktc); return CHAL_DSI_OK; }
/* * * Function Name: chal_dsi_phy_state * * Description: PHY State Control * Controls Clock & Data Line States * * CLK lane cannot be directed to STOP state. It is normally in stop state * if cont clock is not enabled. * CLK lane will not transition to ULPS if cont clk is enabled. * When ULPS is requested and cont clock was enabled it will be disabled * at same time as ULPS is activated, and re-enabled upon ULPS exit * */ cVoid chal_dsi_phy_state(CHAL_HANDLE handle, CHAL_DSI_PHY_STATE_t state) { struct CHAL_DSI *pDev = (struct CHAL_DSI *)handle; cUInt32 regMask = 0; cUInt32 regVal = 0; regMask = DSI_REG_FIELD_SET(DSI1_PHYC, FORCE_TXSTOP_0, 1) | DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSCLK, 1) | DSI_REG_FIELD_SET(DSI1_PHYC, TX_HSCLK_CONT, 1); #if !defined(CONFIG_MACH_HAWAII_FPGA_E) || !defined(CONFIG_MACH_HAWAII_FPGA) switch (pDev->dlCount) { case 4: regMask |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_3, 1); regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_3, 1); case 3: regMask |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_2, 1); regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_2, 1); case 2: regMask |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_1, 1); regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_1, 1); case 1: default: regMask |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_0, 1); regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSESC_0, 1); } #endif switch (state) { case PHY_TXSTOP: regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, FORCE_TXSTOP_0, 1); break; case PHY_ULPS: regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, TXULPSCLK, 1); break; case PHY_CORE: default: if (pDev->clkContinuous) regVal |= DSI_REG_FIELD_SET(DSI1_PHYC, TX_HSCLK_CONT, 1); else regVal = 0; break; } DSI_REG_WRITE_MASKED(pDev->baseAddr, DSI1_PHYC, regMask, regVal); }