static void _WaitForEngineNotBusy(void)
{
int timeOut;
#if ENABLE_DSI_INTERRUPT
long int time;
static const long WAIT_TIMEOUT = 2 * HZ; // 2 sec
#endif
if (DSI_REG->DSI_MODE_CTRL.MODE)
return ;
timeOut = 20;
#if ENABLE_DSI_INTERRUPT
time = get_current_time_us();
if (in_interrupt())
{
// perform busy waiting if in interrupt context
while(_IsEngineBusy()) {
msleep(1);
if (--timeOut < 0) {
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", " Wait for DSI engine not busy timeout!!!(Wait %d us)\n", get_current_time_us() - time);
DSI_DumpRegisters();
DSI_Reset();
break;
}
}
}
else
{
while (_IsEngineBusy())
{
long ret = wait_event_interruptible_timeout(_dsi_wait_queue,
!_IsEngineBusy(),
WAIT_TIMEOUT);
if (0 == ret) {
DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine not busy timeout!!!\n");
}
}
}
#else
while(_IsEngineBusy()) {
msleep(1);
if (--timeOut < 0) {
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", " Wait for DSI engine not busy timeout!!!\n");
DSI_DumpRegisters();
DSI_Reset();
break;
}
}
#endif
}
int disphal_panel_enable(const LCM_DRIVER *lcm_drv, struct mutex* pLcmCmdMutex, BOOL enable)
{
if (enable)
{
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
DSI_SetMode(CMD_MODE);
}
mutex_lock(pLcmCmdMutex);
//#ifdef MTK_DISP_CONFIG_SUPPORT
if(get_fbconfig_start_lcm_config())
{
fbconfig_apply_new_lcm_setting();
//do not call lcm_init if you have ever started LCM config until you reset lcm config ;
}
else
//#endif
lcm_drv->resume();
mutex_unlock(pLcmCmdMutex);
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
//DSI_clk_HS_mode(1);
DSI_WaitForNotBusy();
DSI_SetMode(lcm_params->dsi.mode);
}
}
else
{
LCD_CHECK_RET(LCD_WaitForNotBusy());
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode == CMD_MODE)
DSI_CHECK_RET(DSI_WaitForNotBusy());
if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
DPI_CHECK_RET(DPI_DisableClk());
//msleep(200);
DSI_Reset();
DSI_clk_HS_mode(0);
DSI_SetMode(CMD_MODE);
}
mutex_lock(pLcmCmdMutex);
//#ifdef MTK_DISP_CONFIG_SUPPORT
if(get_fbconfig_start_lcm_config())
{
fbconfig_apply_new_lcm_setting();
//do not call lcm_init if you have ever started LCM config until you reset lcm config ;
}
else
//#endif
lcm_drv->suspend();
mutex_unlock(pLcmCmdMutex);
}
return 0;
}
DISP_STATUS DISP_PanelEnable(BOOL enable)
{
static BOOL s_enabled = FALSE;
disp_drv_init_context();
if (!lcm_drv->suspend || !lcm_drv->resume) {
return DISP_STATUS_NOT_IMPLEMENTED;
}
if (enable && !s_enabled) {
s_enabled = TRUE;
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
DSI_SetMode(CMD_MODE);
}
lcm_drv->resume();
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
//DSI_clk_HS_mode(1);
DSI_SetMode(lcm_params->dsi.mode);
//DPI_CHECK_RET(DPI_EnableClk());
//DSI_CHECK_RET(DSI_EnableClk());
}
}
else if (!enable && s_enabled)
{
LCD_CHECK_RET(LCD_WaitForNotBusy());
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode == CMD_MODE)
DSI_CHECK_RET(DSI_WaitForNotBusy());
s_enabled = FALSE;
if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
DPI_CHECK_RET(DPI_DisableClk());
udelay(200*1000);
DSI_Reset();
DSI_clk_HS_mode(0);
DSI_SetMode(CMD_MODE);
}
lcm_drv->suspend();
}
return DISP_STATUS_OK;
}
// called by "esd_recovery_kthread"
// protected by sem_early_suspend, sem_update_screen
void dsi_esd_reset(void)
{
/// we assume the power is on here
/// what we need is some setting for LCM init
if(lcm_params->dsi.mode == CMD_MODE)
{
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
}
else
{
DSI_SetMode(CMD_MODE);
DSI_clk_HS_mode(0);
// clock/data lane go to Ideal
DSI_Reset();
}
}
static void lcm_suspend(void)
{
unsigned int data_array[16];
dsi_set_cmdq_V3(lcm_initialization_sleep_in_V3, sizeof(lcm_initialization_sleep_in_V3) / sizeof(LCM_setting_table_V3), 1);
MDELAY(120);
lcm_set_pwm_for_mix(0);
MDELAY(16);
DPI_DisableClk();
DSI_Reset();
DSI_clk_HS_mode(1);
DSI_SetMode(0);
/* MDELAY(1); */
dsi_set_cmdq_V3(lcm_suspend_ULPS_for_data0_in_V3, sizeof(lcm_suspend_ULPS_for_data0_in_V3) / sizeof(LCM_setting_table_V3), 1);
MDELAY(200);
LCM_PRINT("[LCD] lcm_suspend\n");
}
static irqreturn_t _DPI_InterruptHandler(int irq, void *dev_id)
{
static int counter = 0;
DPI_REG_INTERRUPT status = DPI_REG->INT_STATUS;
// if (status.FIFO_EMPTY) ++ counter;
if(status.VSYNC)
{
if(dpiIntCallback)
dpiIntCallback(DISP_DPI_VSYNC_INT);
#ifndef BUILD_UBOOT
if(atomic_read(&wait_dpi_vsync)){
if(-1 != hrtimer_try_to_cancel(&hrtimer_vsync_dpi)){
atomic_set(&wait_dpi_vsync, 0);
atomic_set(&dpi_vsync, 1);
wake_up_interruptible(&_vsync_wait_queue_dpi);
hrtimer_start(&hrtimer_vsync_dpi, ktime_set(0, VSYNC_US_TO_NS(vsync_timer_dpi)), HRTIMER_MODE_REL);
}
}
#endif
}
if (status.VSYNC && counter) {
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DPI", "[Error] DPI FIFO is empty, "
"received %d times interrupt !!!\n", counter);
counter = 0;
}
if (status.FIFO_EMPTY)
{
int need_reset = 0;
unsigned long long temp = sched_clock();
unsigned int debug_while_loop_cnt = 0;
volatile unsigned int dsi_state = INREG32(DSI_BASE+0x154);
if((dsi_state & 0x1ff) == 0x80)
{
auto_sync_reset_count++;
if(auto_sync_reset_count == 10)
{
auto_sync_reset_count = 0;
need_reset = 2;
}
}
else
{
auto_sync_reset_count = 0;
}
//printk("gmce,0x%08x, %d\n",(INREG32(DSI_BASE+0x154))&0x1ff, (unsigned int)(temp - last_fifo_empty_stamp));
if(_fifo_empty_monitor_insert((unsigned int)(temp - last_fifo_empty_stamp)))
{
need_reset = 1;
}
last_fifo_empty_stamp = temp;
if(need_reset)
{
unsigned int mode, suspend;
mode = DSI_GetMode();
suspend = DISP_GetSuspendMode();
if ((mode != CMD_MODE) && !suspend)
{
DPI_DisableClk();
#if 0
while(1)
{
debug_while_loop_cnt++;
dsi_state = INREG32(DSI_BASE+0x154);
if((dsi_state &0x1ff) == 0x100) break;
if(debug_while_loop_cnt > 0x1000000)
{
printk("FATAL Error!! dsi in vact when dpi fifo empty, and can't into vfp until 0x100000 loops!!\n");
}
}
#endif
DSI_clk_HS_mode(0);
DSI_SetMode(CMD_MODE);
DSI_Reset();
DSI_SetMode(SYNC_PULSE_VDO_MODE);
DSI_clk_HS_mode(1);
DPI_EnableClk();
DSI_EnableClk();
}
printk("[DSI/DPI]reset[%d] mode[%d], suspend[%d]\n", need_reset, mode, suspend);
need_reset = 0;
}
}
_DPI_LogRefreshRate(status);
OUTREG32(&DPI_REG->INT_STATUS, 0);
return IRQ_HANDLED;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE) {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_WaitForNotBusy();
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_Reset();
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
Wait_WakeUp();
LCD_CHECK_RET(LCD_PowerOn());
#endif
} else {
LCD_CHECK_RET(LCD_PowerOff());
DSI_clk_HS_mode(0);
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
DSI_CHECK_RET(DSI_PowerOff());
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
} else {
#if 0
#ifndef BUILD_UBOOT
spin_lock(&g_handle_esd_lock);
#endif
#endif
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
DSI_Reset();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
Wait_WakeUp();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#endif
} else {
#ifndef BUILD_UBOOT
dsi_vdo_streaming = false;
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
LCD_CHECK_RET(LCD_PowerOff());
DPI_CHECK_RET(DPI_PowerOff());
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
DSI_CHECK_RET(DSI_PowerOff());
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
#if 0
#ifndef BUILD_UBOOT
spin_unlock(&g_handle_esd_lock);
#endif
#endif
}
return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE) {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_WaitForNotBusy();
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_Reset();
LCD_CHECK_RET(LCD_PowerOn());
#else
#ifndef MT65XX_NEW_DISP
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// initialize dsi timing
DSI_PHY_TIMCONFIG(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(TRUE, lcm_params);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
// engine reset
DSI_Reset();
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
#endif
#endif
}
else {
// backup dsi register
DSI_CHECK_RET(DSI_WaitForEngineNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
mdelay(1);
// disable engine clock
DSI_CHECK_RET(DSI_DisableClk());
// disable CG
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(FALSE, lcm_params);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
else {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
DSI_Reset();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#else
#ifndef MT65XX_NEW_DISP
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
needStartDSI = true;
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// initialize dsi timing
DSI_PHY_TIMCONFIG(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(TRUE, lcm_params);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
// engine reset
DSI_Reset();
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
#endif
#endif
}
else {
#ifndef BUILD_UBOOT
is_video_mode_running = false;
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
// backup dsi register
DSI_CHECK_RET(DSI_WaitForEngineNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
mdelay(1);
// disable engine clock
DSI_CHECK_RET(DSI_DisableClk());
// disable CG
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(FALSE, lcm_params);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE) {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_WaitForNotBusy();
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_Reset();
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
#ifndef MT65XX_NEW_DISP
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
if(lcm_params->dsi.pll_select == 1)
{
ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
}
DSI_PHY_clk_setting(lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
// DSI_clk_HS_mode(1);
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
LCD_CHECK_RET(LCD_PowerOn());
#endif
#endif
} else {
#ifndef MT65XX_NEW_DISP
LCD_CHECK_RET(LCD_PowerOff());
#endif
DSI_clk_HS_mode(0);
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
// DSI_CHECK_RET(DSI_PowerOff());
DSI_PHY_clk_switch(0);
DSI_CHECK_RET(DSI_PowerOff());
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
if(lcm_params->dsi.pll_select == 1)
ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
}
} else {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
DSI_Reset();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
#ifndef MT65XX_NEW_DISP
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
needStartDSI = true;
if(lcm_params->dsi.pll_select == 1)
{
ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
}
DSI_PHY_clk_setting(lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#endif
#endif
} else {
#ifndef BUILD_UBOOT
is_video_mode_running = false;
#ifndef MT65XX_NEW_DISP
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
#endif
#ifndef MT65XX_NEW_DISP
LCD_CHECK_RET(LCD_PowerOff());
DPI_CHECK_RET(DPI_PowerOff());
#endif
#if 1
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
DSI_CHECK_RET(DSI_PowerOff());
#endif
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
if(lcm_params->dsi.pll_select == 1)
ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
}
}
return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE)
{
if (enable)
{
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(1);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_Reset();
}
else
{
// backup dsi register
DSI_CHECK_RET(DSI_WaitForNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
DSI_clk_HS_mode(0);
// disable clock
DSI_CHECK_RET(DSI_DisableClk());
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
else
{
if (enable)
{
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(1);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
DSI_clk_HS_mode(0);
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_Reset();
needStartDSI = true;
}
else
{
is_video_mode_running = false;
// backup dsi register
DSI_CHECK_RET(DSI_WaitForNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
// disable clock
DSI_CHECK_RET(DSI_DisableClk());
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
return DISP_STATUS_OK;
}
DISP_STATUS DISP_PanelEnable(BOOL enable)
{
static BOOL s_enabled = TRUE;
DISP_STATUS ret = DISP_STATUS_OK;
DISP_LOG("panel is %s\n", enable?"enabled":"disabled");
if (down_interruptible(&sem_update_screen)) {
DISP_LOG("ERROR: Can't get sem_update_screen in DISP_PanelEnable()\n");
return DISP_STATUS_ERROR;
}
disp_drv_init_context();
is_lcm_in_suspend_mode = enable ? FALSE : TRUE;
if (!lcm_drv->suspend || !lcm_drv->resume) {
ret = DISP_STATUS_NOT_IMPLEMENTED;
goto End;
}
if (enable && !s_enabled) {
s_enabled = TRUE;
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
DSI_SetMode(CMD_MODE);
}
lcm_drv->resume();
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
//DSI_clk_HS_mode(1);
DSI_SetMode(lcm_params->dsi.mode);
//DPI_CHECK_RET(DPI_EnableClk());
//DSI_CHECK_RET(DSI_EnableClk());
msleep(200);
}
}
else if (!enable && s_enabled)
{
LCD_CHECK_RET(LCD_WaitForNotBusy());
if(lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode == CMD_MODE)
DSI_CHECK_RET(DSI_WaitForNotBusy());
s_enabled = FALSE;
if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE)
{
DPI_CHECK_RET(DPI_DisableClk());
//msleep(200);
DSI_Reset();
DSI_clk_HS_mode(0);
DSI_SetMode(CMD_MODE);
}
lcm_drv->suspend();
}
End:
up(&sem_update_screen);
return ret;
}
