static int board_setup(void)
{
sysinfo_install_flags();
Exynos5420Gpio *lid_switch = new_exynos5420_gpio_input(GPIO_X, 3, 4);
Exynos5420Gpio *ec_in_rw = new_exynos5420_gpio_input(GPIO_X, 2, 3);
flag_replace(FLAG_LIDSW, &lid_switch->ops);
flag_install(FLAG_ECINRW, &ec_in_rw->ops);
// The power switch is active low and needs to be inverted.
Exynos5420Gpio *power_switch_l =
new_exynos5420_gpio_input(GPIO_X, 1, 2);
flag_replace(FLAG_PWRSW, new_gpio_not(&power_switch_l->ops));
Exynos5UsiI2c *i2c9 = new_exynos5_usi_i2c(0x12e10000, 400000);
tpm_set_ops(&new_slb9635_i2c(&i2c9->ops, 0x20)->base.ops);
Exynos5Spi *spi1 = new_exynos5_spi(0x12d30000);
Exynos5Spi *spi2 = new_exynos5_spi(0x12d40000);
CrosEcSpiBus *cros_ec_spi_bus = new_cros_ec_spi_bus(&spi2->ops);
cros_ec_set_bus(&cros_ec_spi_bus->ops);
flash_set_ops(&new_spi_flash(&spi1->ops, 0x400000)->ops);
Exynos5I2s *i2s0 = new_exynos5_i2s_multi(0x03830000, 16, 2, 256);
I2sSource *i2s_source = new_i2s_source(&i2s0->ops, 48000, 2, 16000);
sound_set_ops(&new_sound_route(&i2s_source->ops)->ops);
DwmciHost *emmc = new_dwmci_host(0x12200000, 100000000, 8, 0,
DWMCI_SET_SAMPLE_CLK(1) |
DWMCI_SET_DRV_CLK(3) |
DWMCI_SET_DIV_RATIO(3));
DwmciHost *sd_card = new_dwmci_host(0x12220000, 100000000, 4, 1,
DWMCI_SET_SAMPLE_CLK(1) |
DWMCI_SET_DRV_CLK(2) |
DWMCI_SET_DIV_RATIO(3));
list_insert_after(&emmc->mmc.ctrlr.list_node,
&fixed_block_dev_controllers);
list_insert_after(&sd_card->mmc.ctrlr.list_node,
&removable_block_dev_controllers);
power_set_ops(&exynos_power_ops);
UsbHostController *usb_drd0 = new_usb_hc(XHCI, 0x12000000);
UsbHostController *usb_drd1 = new_usb_hc(XHCI, 0x12400000);
set_usb_init_callback(usb_drd0, exynos5420_usbss_phy_tune);
/* DRD1 port has no SuperSpeed lines anyway */
list_insert_after(&usb_drd0->list_node, &usb_host_controllers);
list_insert_after(&usb_drd1->list_node, &usb_host_controllers);
return 0;
}
static void dw_mci_clksel(struct dwmci_host *host)
{
u32 val;
val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
dwmci_writel(host, DWMCI_CLKSEL, val);
}
int exynos_dwmmc_init(const void *blob)
{
int index, bus_width;
int node_list[DWMMC_MAX_CH_NUM];
int err = 0, dev_id, flag, count, i;
u32 clksel_val, base, timing[3];
count = fdtdec_find_aliases_for_id(blob, "mmc",
COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
DWMMC_MAX_CH_NUM);
for (i = 0; i < count; i++) {
int node = node_list[i];
if (node <= 0)
continue;
/* Extract device id for each mmc channel */
dev_id = pinmux_decode_periph_id(blob, node);
/* Get the bus width from the device node */
bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (bus_width <= 0) {
debug("DWMMC: Can't get bus-width\n");
return -1;
}
if (8 == bus_width)
flag = PINMUX_FLAG_8BIT_MODE;
else
flag = PINMUX_FLAG_NONE;
/* config pinmux for each mmc channel */
err = exynos_pinmux_config(dev_id, flag);
if (err) {
debug("DWMMC not configured\n");
return err;
}
index = dev_id - PERIPH_ID_SDMMC0;
/* Get the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
debug("DWMMC: Can't get base address\n");
return -1;
}
/* Extract the timing info from the node */
err = fdtdec_get_int_array(blob, node, "samsung,timing",
timing, 3);
if (err) {
debug("Can't get sdr-timings for divider\n");
return -1;
}
clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
DWMCI_SET_DRV_CLK(timing[1]) |
DWMCI_SET_DIV_RATIO(timing[2]));
/* Initialise each mmc channel */
err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
if (err)
debug("dwmmc Channel-%d init failed\n", index);
}
return 0;
}
