Example #1
0
void circuits( SD sd, Signal Init, Signal Clock, 
  Signal w, Signal x, Signal y, Signal z )
{
  Module( (sd, "circuits"), (Init, Clock), (w, x, y, z) );

  // Insert your declarations for any auxiliary Signals here
  
  Signal W, X, Y, Z;

  // Insert your DFFs here
  
  Dff( SD("1b"), ( Init, W, Clock, Zero ), w );
  Dff( SD("2b"), ( Zero, X, Clock, Init ), x );
  Dff( SD("3b"), ( Init, Y, Clock, Zero ), y );
  Dff( SD("4b"), ( Zero, Z, Clock, Init ), z );

  // Insert your combinational logic here (Not, And, Or gates)
  
  Signal notx, noty, notz;
  Not ( SD(sd,"1d"), x, notx );
  Not ( SD(sd,"2d"), y, noty );
  Not ( SD(sd,"3d"), z, notz );
  
  Signal and1, and2, and3, and4;
  And ( SD(sd,"1e"), (notx, noty), and1 );
  And ( SD(sd,"2e"), (x, notz), and2 );                                        
  And ( SD(sd,"3e"), (w, y), and3 ); 
  And ( SD(sd,"4e"), (noty, notz), and4 );
  
  Or ( SD(sd,"1f"), (and1, and1), W ); 
  Or ( SD(sd,"2f"), (and2, and3), X ); 
  Or ( SD(sd,"3f"), (z, z), Y ); 
  Or ( SD(sd,"4f"), (and4, and4), Z ); 

}
void circuits( SD sd, Signal Init, Signal Clock, 
  Signal w, Signal x, Signal y, Signal z )
{
  Module( (sd, "circuits"), (Init, Clock), (w, x, y, z) );

  // Insert your declarations for any auxiliary Signals here
  Signal notw, notx, noty, notz, W, X, Y, Z;
  // Insert your DFFs here
  Dff (SD(sd,"2g"), (Init, W, Clock, Zero), w);
  Dff (SD(sd,"3g"), (Zero, X, Clock, Init), x);
  Dff (SD(sd,"4g"), (Init, Y, Clock, Zero), y);
  Dff (SD(sd,"5g"), (Zero, Z, Clock, Init), z);

  // Insert your combinational logic here (Not, And, Or gates)
  Not (SD(sd,"2b"), w, notw);
  Not (SD(sd,"3b"), x, notx);
  Not (SD(sd,"4b"), y, noty);
  Not (SD(sd,"5b"), z, notz);



  // W = wx + yz + wy' 
  Signal wfirst, wsecond, wthird;
  And (SD(sd, "2c"), (w, x), wfirst);
  And (SD(sd, "3c"), (y, z), wsecond);
  And (SD(sd, "4c"), (w, noty), wthird);
  Or (SD(sd, "5c"), (wfirst, wsecond, wthird), W);


  // X = xz' + wz + wy
  Signal xfirst, xsecond, xthird;
  And (SD(sd, "2d"), (x, notz), xfirst);
  And (SD(sd, "3d"), (w, z), xsecond);
  And (SD(sd, "4d"), (w, y), xthird);
  Or (SD(sd, "6d"), (xfirst, xsecond, xthird), X);

  // Y = y'z + xy + wy'
  Signal yfirst, ysecond, ythird;
  And (SD(sd, "2e"), (noty, z), yfirst);
  And (SD(sd, "3e"), (x, y), ysecond);
  And (SD(sd, "4e"), (w, noty), ythird); 
  Or (SD(sd, "5e"), (yfirst, ysecond, ythird), Y);

  // Z = wx + w'z' + x'y'z 
  Signal zfirst, zsecond, zthird;
  And (SD(sd, "2f"), (w, x), zfirst);
  And (SD(sd, "3f"), (notw, notz), zsecond);
  And (SD(sd, "4f"), (notx, noty, z), zthird);
  Or (SD(sd, "5f"), (zfirst, zsecond, zthird), Z);
}