Example #1
0
/**
 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Tx unit of the MAC after a reset.
 **/
static void e1000_configure_tx ( struct e1000_adapter *adapter )
{
	struct e1000_hw *hw = &adapter->hw;
	uint32_t tctl;

	DBG ( "e1000_configure_tx\n" );

	E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
	E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
	E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );

        DBG ( "E1000_TDBAL(0): %#08x\n",  E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
        DBG ( "E1000_TDLEN(0): %d\n",     E1000_READ_REG ( hw, E1000_TDLEN(0) ) );

	/* Setup the HW Tx Head and Tail descriptor pointers */
	E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
	E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );

	adapter->tx_head = 0;
	adapter->tx_tail = 0;
	adapter->tx_fill_ctr = 0;

	/* Setup Transmit Descriptor Settings for eop descriptor */
	tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
		(E1000_COLLISION_DISTANCE  << E1000_COLD_SHIFT);

	e1000_config_collision_dist ( hw );

	E1000_WRITE_REG ( hw, E1000_TCTL, tctl );
        E1000_WRITE_FLUSH ( hw );
}
Example #2
0
/*------------------------------------------------------------------------
 * _82545EM_configure_tx - Configure Transmit Unit after Reset
 *------------------------------------------------------------------------
 */
local void _82545EM_configure_tx(
	struct 	ether *ethptr
	)
{
	uint32 	tctl, tipg, txdctl;
	uint32 	ipgr1, ipgr2;

	/* Set the transmit descriptor write-back policy for both queues */

	txdctl = e1000_io_readl(ethptr->iobase, E1000_TXDCTL(0));
	txdctl &= ~E1000_TXDCTL_WTHRESH;
	txdctl |= E1000_TXDCTL_GRAN;
	e1000_io_writel(ethptr->iobase, E1000_TXDCTL(0), txdctl);

	/* Program the Transmit Control Register */
	
	tctl = e1000_io_readl(ethptr->iobase, E1000_TCTL);
	tctl &= ~E1000_TCTL_CT;
	tctl |= E1000_TCTL_RTLC |
		E1000_TCTL_EN 	|
		E1000_TCTL_PSP 	|
		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
	tctl &= ~E1000_TCTL_COLD;
	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;

	/* Set the default values for the Tx Inter Packet Gap timer */
	
	tipg = E1000_TIPG_IPGT_COPPER_DEFAULT;
	ipgr1 = E1000_TIPG_IPGR1_DEFAULT;
	ipgr2 = E1000_TIPG_IPGR2_DEFAULT;
	tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
	tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
	e1000_io_writel(ethptr->iobase, E1000_TIPG, tipg);

	/* Set the Tx Interrupt Delay register */
	
	e1000_io_writel(ethptr->iobase, E1000_TIDV, E1000_TIDV_DEFAULT);
	e1000_io_writel(ethptr->iobase, E1000_TADV, E1000_TADV_DEFAULT);

	/* Setup the HW Tx Head and Tail descriptor pointers */
	
	e1000_io_writel(ethptr->iobase, E1000_TDBAL(0), 
			(uint32)ethptr->txRing);
	e1000_io_writel(ethptr->iobase, E1000_TDBAH(0), 0);
	e1000_io_writel(ethptr->iobase, E1000_TDLEN(0), 
			E1000_TDSIZE * ethptr->txRingSize);
	e1000_io_writel(ethptr->iobase, E1000_TDH(0), 0);
	e1000_io_writel(ethptr->iobase, E1000_TDT(0), 0);

	e1000_io_writel(ethptr->iobase, E1000_TCTL, tctl);
}
Example #3
0
/**
 *  e1000_translate_register_82542 - Translate the proper register offset
 *  @reg: e1000 register to be read
 *
 *  Registers in 82542 are located in different offsets than other adapters
 *  even though they function in the same manner.  This function takes in
 *  the name of the register to read and returns the correct offset for
 *  82542 silicon.
 **/
u32 e1000_translate_register_82542(u32 reg)
{
    /*
     * Some of the 82542 registers are located at different
     * offsets than they are in newer adapters.
     * Despite the difference in location, the registers
     * function in the same manner.
     */
    switch (reg) {
    case E1000_RA:
        reg = 0x00040;
        break;
    case E1000_RDTR:
        reg = 0x00108;
        break;
    case E1000_RDBAL(0):
        reg = 0x00110;
        break;
    case E1000_RDBAH(0):
        reg = 0x00114;
        break;
    case E1000_RDLEN(0):
        reg = 0x00118;
        break;
    case E1000_RDH(0):
        reg = 0x00120;
        break;
    case E1000_RDT(0):
        reg = 0x00128;
        break;
    case E1000_RDBAL(1):
        reg = 0x00138;
        break;
    case E1000_RDBAH(1):
        reg = 0x0013C;
        break;
    case E1000_RDLEN(1):
        reg = 0x00140;
        break;
    case E1000_RDH(1):
        reg = 0x00148;
        break;
    case E1000_RDT(1):
        reg = 0x00150;
        break;
    case E1000_FCRTH:
        reg = 0x00160;
        break;
    case E1000_FCRTL:
        reg = 0x00168;
        break;
    case E1000_MTA:
        reg = 0x00200;
        break;
    case E1000_TDBAL(0):
        reg = 0x00420;
        break;
    case E1000_TDBAH(0):
        reg = 0x00424;
        break;
    case E1000_TDLEN(0):
        reg = 0x00428;
        break;
    case E1000_TDH(0):
        reg = 0x00430;
        break;
    case E1000_TDT(0):
        reg = 0x00438;
        break;
    case E1000_TIDV:
        reg = 0x00440;
        break;
    case E1000_VFTA:
        reg = 0x00600;
        break;
    case E1000_TDFH:
        reg = 0x08010;
        break;
    case E1000_TDFT:
        reg = 0x08018;
        break;
    default:
        break;
    }

    return reg;
}
Example #4
0
File: ethtool.c Project: A-K/linux
static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
{
	struct e1000_hw *hw = &adapter->hw;
	struct e1000_mac_info *mac = &adapter->hw.mac;
	u32 value;
	u32 before;
	u32 after;
	u32 i;
	u32 toggle;
	u32 mask;
	u32 wlock_mac = 0;

	/*
	 * The status register is Read Only, so a write should fail.
	 * Some bits that get toggled are ignored.
	 */
	switch (mac->type) {
	/* there are several bits on newer hardware that are r/w */
	case e1000_82571:
	case e1000_82572:
	case e1000_80003es2lan:
		toggle = 0x7FFFF3FF;
		break;
        default:
		toggle = 0x7FFFF033;
		break;
	}

	before = er32(STATUS);
	value = (er32(STATUS) & toggle);
	ew32(STATUS, toggle);
	after = er32(STATUS) & toggle;
	if (value != after) {
		e_err("failed STATUS register test got: 0x%08X expected: 0x%08X\n",
		      after, value);
		*data = 1;
		return 1;
	}
	/* restore previous status */
	ew32(STATUS, before);

	if (!(adapter->flags & FLAG_IS_ICH)) {
		REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
		REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
		REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
		REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
	}

	REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
	REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
	REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF);
	REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF);
	REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF);
	REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
	REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
	REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
	REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
	REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF);

	REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);

	before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);
	REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
	REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);

	REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
	REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
	if (!(adapter->flags & FLAG_IS_ICH))
		REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
	REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
	REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
	mask = 0x8003FFFF;
	switch (mac->type) {
	case e1000_ich10lan:
	case e1000_pchlan:
	case e1000_pch2lan:
	case e1000_pch_lpt:
		mask |= (1 << 18);
		break;
	default:
		break;
	}

	if (mac->type == e1000_pch_lpt)
		wlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >>
		    E1000_FWSM_WLOCK_MAC_SHIFT;

	for (i = 0; i < mac->rar_entry_count; i++) {
		/* Cannot test write-protected SHRAL[n] registers */
		if ((wlock_mac == 1) || (wlock_mac && (i > wlock_mac)))
			continue;

		REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
				       mask, 0xFFFFFFFF);
	}

	for (i = 0; i < mac->mta_reg_count; i++)
		REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);

	*data = 0;

	return 0;
}
Example #5
0
/**
 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Tx unit of the MAC after a reset.
 **/
static void e1000e_configure_tx ( struct e1000_adapter *adapter )
{
	struct e1000_hw *hw = &adapter->hw;
	u32 tctl, tipg, tarc;
	u32 ipgr1, ipgr2;

	DBGP ( "e1000_configure_tx\n" );

	/* disable transmits while setting up the descriptors */
	tctl = E1000_READ_REG ( hw, E1000_TCTL );
	E1000_WRITE_REG ( hw, E1000_TCTL, tctl & ~E1000_TCTL_EN );
	e1e_flush();
	mdelay(10);

	E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
	E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
	E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );

	DBG ( "E1000_TDBAL(0): %#08x\n",  E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
	DBG ( "E1000_TDLEN(0): %d\n",	  E1000_READ_REG ( hw, E1000_TDLEN(0) ) );

	/* Setup the HW Tx Head and Tail descriptor pointers */
	E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
	E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );

	adapter->tx_head = 0;
	adapter->tx_tail = 0;
	adapter->tx_fill_ctr = 0;

	/* Set the default values for the Tx Inter Packet Gap timer */
	tipg = DEFAULT_82543_TIPG_IPGT_COPPER;		/*  8  */
	ipgr1 = DEFAULT_82543_TIPG_IPGR1;		/*  8  */
	ipgr2 = DEFAULT_82543_TIPG_IPGR2;		/*  6  */

	if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
		ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /*  7  */

	tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
	tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
	ew32(TIPG, tipg);

	/* Program the Transmit Control Register */
	tctl = er32(TCTL);
	tctl &= ~E1000_TCTL_CT;
	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);

	if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
		tarc = er32(TARC(0));
		/*
		 * set the speed mode bit, we'll clear it if we're not at
		 * gigabit link later
		 */
#define SPEED_MODE_BIT (1 << 21)
		tarc |= SPEED_MODE_BIT;
		ew32(TARC(0), tarc);
	}

	/* errata: program both queues to unweighted RR */
	if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
		tarc = er32(TARC(0));
		tarc |= 1;
		ew32(TARC(0), tarc);
		tarc = er32(TARC(1));
		tarc |= 1;
		ew32(TARC(1), tarc);
	}

	/* Setup Transmit Descriptor Settings for eop descriptor */
	adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;

	/* enable Report Status bit */
	adapter->txd_cmd |= E1000_TXD_CMD_RS;

	/*
	 * enable transmits in the hardware, need to do this
	 * after setting TARC(0)
	 */
	tctl |= E1000_TCTL_EN;
	ew32(TCTL, tctl);
	e1e_flush();

	e1000e_config_collision_dist(hw);
}
Example #6
0
/*
 * mac_dump - dump important mac registers
 */
void
mac_dump(void *instance)
{
    struct e1000g *Adapter = (struct e1000g *)instance;
    struct e1000_hw *hw = &Adapter->shared;
    int i;

    /* {name, offset} for each mac register */
    Regi_t macreg[NUM_REGS] = {
        {"CTRL",	E1000_CTRL},	{"STATUS",	E1000_STATUS},
        {"EECD",	E1000_EECD},	{"EERD",	E1000_EERD},
        {"CTRL_EXT", E1000_CTRL_EXT}, {"FLA",	E1000_FLA},
        {"MDIC",	E1000_MDIC},	{"SCTL",	E1000_SCTL},
        {"FCAL",	E1000_FCAL},	{"FCAH",	E1000_FCAH},
        {"FCT",	E1000_FCT},	{"VET",		E1000_VET},
        {"ICR",	E1000_ICR},	{"ITR",		E1000_ITR},
        {"ICS",	E1000_ICS},	{"IMS",		E1000_IMS},
        {"IMC",	E1000_IMC},	{"IAM",		E1000_IAM},
        {"RCTL",	E1000_RCTL},	{"FCTTV",	E1000_FCTTV},
        {"TXCW",	E1000_TXCW},	{"RXCW",	E1000_RXCW},
        {"TCTL",	E1000_TCTL},	{"TIPG",	E1000_TIPG},
        {"AIT",	E1000_AIT},	{"LEDCTL",	E1000_LEDCTL},
        {"PBA",	E1000_PBA},	{"PBS",		E1000_PBS},
        {"EEMNGCTL", E1000_EEMNGCTL}, {"ERT",	E1000_ERT},
        {"FCRTL",	E1000_FCRTL},	{"FCRTH",	E1000_FCRTH},
        {"PSRCTL",	E1000_PSRCTL},	{"RDBAL(0)",	E1000_RDBAL(0)},
        {"RDBAH(0)", E1000_RDBAH(0)}, {"RDLEN(0)",	E1000_RDLEN(0)},
        {"RDH(0)",	E1000_RDH(0)},	{"RDT(0)",	E1000_RDT(0)},
        {"RDTR",	E1000_RDTR},	{"RXDCTL(0)",	E1000_RXDCTL(0)},
        {"RADV",	E1000_RADV},	{"RDBAL(1)",	E1000_RDBAL(1)},
        {"RDBAH(1)", E1000_RDBAH(1)}, {"RDLEN(1)",	E1000_RDLEN(1)},
        {"RDH(1)",	E1000_RDH(1)},	{"RDT(1)",	E1000_RDT(1)},
        {"RXDCTL(1)", E1000_RXDCTL(1)}, {"RSRPD",	E1000_RSRPD},
        {"RAID",	E1000_RAID},	{"CPUVEC",	E1000_CPUVEC},
        {"TDFH",	E1000_TDFH},	{"TDFT",	E1000_TDFT},
        {"TDFHS",	E1000_TDFHS},	{"TDFTS",	E1000_TDFTS},
        {"TDFPC",	E1000_TDFPC},	{"TDBAL(0)",	E1000_TDBAL(0)},
        {"TDBAH(0)", E1000_TDBAH(0)}, {"TDLEN(0)",	E1000_TDLEN(0)},
        {"TDH(0)",	E1000_TDH(0)},	{"TDT(0)",	E1000_TDT(0)},
        {"TIDV",	E1000_TIDV},	{"TXDCTL(0)",	E1000_TXDCTL(0)},
        {"TADV",	E1000_TADV},	{"TARC(0)",	E1000_TARC(0)},
        {"TDBAL(1)", E1000_TDBAL(1)}, {"TDBAH(1)",	E1000_TDBAH(1)},
        {"TDLEN(1)", E1000_TDLEN(1)}, {"TDH(1)",	E1000_TDH(1)},
        {"TDT(1)",	E1000_TDT(1)},	{"TXDCTL(1)",	E1000_TXDCTL(1)},
        {"TARC(1)",	E1000_TARC(1)},	{"ALGNERRC",	E1000_ALGNERRC},
        {"RXERRC",	E1000_RXERRC},	{"MPC",		E1000_MPC},
        {"SCC",	E1000_SCC},	{"ECOL",	E1000_ECOL},
        {"MCC",	E1000_MCC},	{"LATECOL",	E1000_LATECOL},
        {"COLC",	E1000_COLC},	{"DC",		E1000_DC},
        {"TNCRS",	E1000_TNCRS},	{"SEC",		E1000_SEC},
        {"CEXTERR",	E1000_CEXTERR},	{"RLEC",	E1000_RLEC},
        {"XONRXC",	E1000_XONRXC},	{"XONTXC",	E1000_XONTXC},
        {"XOFFRXC",	E1000_XOFFRXC},	{"XOFFTXC",	E1000_XOFFTXC},
        {"FCRUC",	E1000_FCRUC},	{"PRC64",	E1000_PRC64},
        {"PRC127",	E1000_PRC127},	{"PRC255",	E1000_PRC255},
        {"PRC511",	E1000_PRC511},	{"PRC1023",	E1000_PRC1023},
        {"PRC1522",	E1000_PRC1522},	{"GPRC",	E1000_GPRC},
        {"BPRC",	E1000_BPRC},	{"MPRC",	E1000_MPRC},
        {"GPTC",	E1000_GPTC},	{"GORCL",	E1000_GORCL},
        {"GORCH",	E1000_GORCH},	{"GOTCL",	E1000_GOTCL},
        {"GOTCH",	E1000_GOTCH},	{"RNBC",	E1000_RNBC},
        {"RUC",	E1000_RUC},	{"RFC",		E1000_RFC},
        {"ROC",	E1000_ROC},	{"RJC",		E1000_RJC},
        {"MGTPRC",	E1000_MGTPRC},	{"MGTPDC",	E1000_MGTPDC},
        {"MGTPTC",	E1000_MGTPTC},	{"TORL",	E1000_TORL},
        {"TORH",	E1000_TORH},	{"TOTL",	E1000_TOTL},
        {"TOTH",	E1000_TOTH},	{"TPR",		E1000_TPR},
        {"TPT",	E1000_TPT},	{"PTC64",	E1000_PTC64},
        {"PTC127",	E1000_PTC127},	{"PTC255",	E1000_PTC255},
        {"PTC511",	E1000_PTC511},	{"PTC1023",	E1000_PTC1023},
        {"PTC1522",	E1000_PTC1522},	{"MPTC",	E1000_MPTC},
        {"BPTC",	E1000_BPTC},	{"TSCTC",	E1000_TSCTC},
        {"TSCTFC",	E1000_TSCTFC},	{"IAC",		E1000_IAC},
        {"ICRXPTC",	E1000_ICRXPTC},	{"ICRXATC",	E1000_ICRXATC},
        {"ICTXPTC",	E1000_ICTXPTC},	{"ICTXATC",	E1000_ICTXATC},
        {"ICTXQEC",	E1000_ICTXQEC},	{"ICTXQMTC",	E1000_ICTXQMTC},
        {"ICRXDMTC", E1000_ICRXDMTC}, {"ICRXOC",	E1000_ICRXOC},
        {"RXCSUM",	E1000_RXCSUM},	{"RFCTL",	E1000_RFCTL},
        {"WUC",	E1000_WUC},	{"WUFC",	E1000_WUFC},
        {"WUS",	E1000_WUS},	{"MRQC",	E1000_MRQC},
        {"MANC",	E1000_MANC},	{"IPAV",	E1000_IPAV},
        {"MANC2H",	E1000_MANC2H},	{"RSSIM",	E1000_RSSIM},
        {"RSSIR",	E1000_RSSIR},	{"WUPL",	E1000_WUPL},
        {"GCR",	E1000_GCR},	{"GSCL_1",	E1000_GSCL_1},
        {"GSCL_2",	E1000_GSCL_2},	{"GSCL_3",	E1000_GSCL_3},
        {"GSCL_4",	E1000_GSCL_4},	{"FACTPS",	E1000_FACTPS},
        {"FWSM",	E1000_FWSM},
    };

    e1000g_log(Adapter, CE_CONT, "Begin MAC dump\n");

    for (i = 0; i < NUM_REGS; i++) {
        e1000g_log(Adapter, CE_CONT,
                   "macreg %10s offset: 0x%x   value: 0x%x\n",
                   macreg[i].name, macreg[i].offset,
                   e1000_read_reg(hw, macreg[i].offset));
    }
}