/*! * @fn void corei7_unc_Write_PMU(param) * * @param param dummy parameter which is not used * * @return None No return needed * * @brief Initial set up of the PMU registers * * <I>Special Notes</I> * Initial write of PMU registers. * Walk through the enties and write the value of the register accordingly. * Assumption: For CCCR registers the enable bit is set to value 0. * When current_group = 0, then this is the first time this routine is called, * initialize the locks and set up EM tables. */ static VOID corei7_unc_Write_PMU ( VOID *param ) { U32 dev_idx = *((U32*)param); FOR_EACH_REG_ENTRY_UNC(pecb_unc, dev_idx, i) { /* * Writing the GLOBAL Control register enables the PMU to start counting. * So write 0 into the register to prevent any counting from starting. */ if (ECB_entries_reg_id(pecb_unc,i) == UNC_UCLK_PERF_GLOBAL_CTRL) { SYS_Write_MSR(ECB_entries_reg_id(pecb_unc,i), 0LL); continue; } SYS_Write_MSR(ECB_entries_reg_id(pecb_unc,i), ECB_entries_reg_value(pecb_unc,i)); #if defined(MYDEBUG) SEP_PRINT_DEBUG("corei7_UNC_Write_PMU Event_Data_reg = 0x%x --- value 0x%llx\n", ECB_entries_reg_id(pecb_unc,i), ECB_entries_reg_value(pecb_unc,i)); #endif // this is needed for overflow detection of the accumulators. if (LWPMU_DEVICE_counter_mask(&devices[dev_idx]) == 0) { LWPMU_DEVICE_counter_mask(&devices[dev_idx]) = (U64)ECB_entries_max_bits(pecb_unc,i); } } END_FOR_EACH_REG_ENTRY_UNC; return; }
/*! * @fn void silvermont_Write_PMU(param) * * @param param dummy parameter which is not used * * @return None No return needed * * @brief Initial set up of the PMU registers * * <I>Special Notes</I> * Initial write of PMU registers. * Walk through the enties and write the value of the register accordingly. * Assumption: For CCCR registers the enable bit is set to value 0. * When current_group = 0, then this is the first time this routine is called, * initialize the locks and set up EM tables. */ static VOID silvermont_Write_PMU ( VOID *param ) { U32 this_cpu = CONTROL_THIS_CPU(); CPU_STATE pcpu = &pcb[this_cpu]; if (CPU_STATE_current_group(pcpu) == 0) { if (EVENT_CONFIG_mode(global_ec) != EM_DISABLED) { U32 index; U32 st_index; U32 j; /* Save all the initialization values away into an array for Event Multiplexing. */ for (j = 0; j < EVENT_CONFIG_num_groups(global_ec); j++) { CPU_STATE_current_group(pcpu) = j; st_index = CPU_STATE_current_group(pcpu) * EVENT_CONFIG_max_gp_events(global_ec); FOR_EACH_DATA_GP_REG(pecb, i) { index = st_index + (ECB_entries_reg_id(pecb,i) - IA32_FULL_PMC0); CPU_STATE_em_tables(pcpu)[index] = ECB_entries_reg_value(pecb,i); } END_FOR_EACH_DATA_GP_REG; } /* Reset the current group to the very first one. */ CPU_STATE_current_group(pcpu) = this_cpu % EVENT_CONFIG_num_groups(global_ec); }
/*! * @fn void corei7_Enable_PMU(param) * * @param param dummy parameter which is not used * * @return None No return needed * * @brief Set the enable bit for all the Control registers * */ static VOID corei7_unc_Enable_PMU ( PVOID param ) { /* * Get the value from the event block * 0 == location of the global control reg for this block. * Generalize this location awareness when possible */ ECB pecb_unc; U32 dev_idx = *((U32*)param); pecb_unc = LWPMU_DEVICE_PMU_register_data(&devices[dev_idx])[0]; if (GLOBAL_STATE_current_phase(driver_state) == DRV_STATE_RUNNING) { SYS_Write_MSR(UNC_UCLK_PERF_GLOBAL_CTRL, ECB_entries_reg_value(pecb_unc,0)); } return; }