/*
mode is enum:
EDMA3_DRV_TRIG_MODE_MANUAL,
EDMA3_DRV_TRIG_MODE_QDMA,
EDMA3_DRV_TRIG_MODE_EVENT,
EDMA3_DRV_TRIG_MODE_NONE
*/
int enable_transfer(unsigned chId, EDMA3_DRV_TrigMode mode)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
result = EDMA3_DRV_enableTransfer (hEdma, chId, mode);
if (result != EDMA3_DRV_SOK)
{
printf("enable_transfer failed: %u\n", chId);
return -1;
}
return 0;
}
// **************************************************************************************
EDMA3_DRV_Result edmaInitiateXfer(const void *dst, const void *src, const int aCnt,
const int bCnt, const int cCnt, const int srcBIdx,
const int destBIdx, const int srcCIdx,
const int destCIdx, const int chCnt)
{
EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
signed char *srcBuf, *dstBuf;
volatile int coreCnt = determineProcId();
EDMA3_DRV_PaRAMRegs paramSet;
srcBuf = (signed char*) getGlobalAddr((signed char *) src);
dstBuf = (signed char*) getGlobalAddr((signed char *) dst);
paramSet.srcAddr = (unsigned int) srcBuf;
paramSet.destAddr = (unsigned int) dstBuf;
paramSet.aCnt = aCnt;
paramSet.bCnt = bCnt;
paramSet.cCnt = cCnt;
paramSet.srcBIdx = srcBIdx;
paramSet.destBIdx = destBIdx;
paramSet.srcCIdx = srcCIdx;
paramSet.destCIdx = destCIdx;
paramSet.bCntReload = 0;
paramSet.linkAddr = 0xFFFFu;
paramSet.opt = 0x00000000u;
// enable final interrupt
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
// set TCC
paramSet.opt |= ((gEdmaXfer[coreCnt][chCnt].tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);
// AB Sync Transfer Mode
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
// prevent a NULL transfer from being submitted; convert it into a dummy transfer
if((aCnt==0) && (bCnt==0)) paramSet.aCnt = 1;
/* Now, write the PaRAM Set. */
edmaResult = EDMA3_DRV_setPaRAM(gHEdma[coreCnt/4], gEdmaXfer[coreCnt][chCnt].chId,
(EDMA3_DRV_PaRAMRegs *) ¶mSet);
// start transfer
if(edmaResult == EDMA3_DRV_SOK)
{
edmaResult = EDMA3_DRV_enableTransfer (gHEdma[coreCnt/4], gEdmaXfer[coreCnt][chCnt].chId,
EDMA3_DRV_TRIG_MODE_MANUAL);
}
return(edmaResult);
} // edmaInitiateXfer
/**
* \brief EDMA3 mem-to-mem data copy test case, using two DMA
* channels, linked to each other.
*
* \param acnt [IN] Number of bytes in an array
* \param bcnt [IN] Number of arrays in a frame
* \param ccnt [IN] Number of frames in a block
* \param syncType [IN] Synchronization type (A/AB Sync)
*
* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
*/
EDMA3_DRV_Result edma3_test_with_link(
EDMA3_DRV_Handle hEdma,
unsigned int acnt,
unsigned int bcnt,
unsigned int ccnt,
EDMA3_DRV_SyncType syncType)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
unsigned int ch1Id = 0;
unsigned int ch2Id = 0;
unsigned int tcc1 = 0;
unsigned int tcc2 = 0;
int i;
unsigned int count;
unsigned int Istestpassed1 = 0u;
unsigned int Istestpassed2 = 0u;
unsigned int numenabled = 0;
unsigned int BRCnt = 0;
int srcbidx = 0, desbidx = 0;
int srccidx = 0, descidx = 0;
srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
srcBuff2 = (signed char*) GLOBAL_ADDR(_srcBuff2);
dstBuff2 = (signed char*) GLOBAL_ADDR(_dstBuff2);
/* Initalize source and destination buffers */
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
{
srcBuff1[count] = (int)count+1;
srcBuff2[count] = (int)count+1;
/**
* No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
dstBuff2[count] = initval;
*/
}
#ifdef EDMA3_ENABLE_DCACHE
/*
* Note: These functions are required if the buffer is in DDR.
* For other cases, where buffer is NOT in DDR, user
* may or may not require the below functions.
*/
/* Flush the Source Buffers */
if (result == EDMA3_DRV_SOK)
{
result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
}
if (result == EDMA3_DRV_SOK)
{
result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));
}
/* Invalidate the Destination Buffers */
if (result == EDMA3_DRV_SOK)
{
result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
}
if (result == EDMA3_DRV_SOK)
{
result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));
}
#endif /* EDMA3_ENABLE_DCACHE */
irqRaised1 = 0;
irqRaised2 = 0;
/* Set B count reload as B count. */
BRCnt = bcnt;
/* Setting up the SRC/DES Index */
srcbidx = (int)acnt;
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
{
/* A Sync Transfer Mode */
srccidx = (int)acnt;
descidx = (int)acnt;
}
else
{
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
}
/* Setup for Channel 1*/
tcc1 = EDMA3_DRV_TCC_ANY;
ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
/* Request any DMA channel and any TCC */
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
(EDMA3_RM_EventQueue)0,
&callback1, NULL);
}
if (result == EDMA3_DRV_SOK)
{
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (unsigned int)(srcBuff1);
paramSet.destAddr = (unsigned int)(dstBuff1);
/**
* Be Careful !!!
* Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767
* Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767
*/
paramSet.srcBIdx = srcbidx;
paramSet.destBIdx = desbidx;
paramSet.srcCIdx = srccidx;
paramSet.destCIdx = descidx;
/**
* Be Careful !!!
* Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
* ACNT/BCNT/CCNT must be greater than or equal to 1.
* Maximum number of bytes in an array (ACNT) is 65535 bytes
* Maximum number of arrays in a frame (BCNT) is 65535
* Maximum number of frames in a block (CCNT) is 65535
*/
paramSet.aCnt = acnt;
paramSet.bCnt = bcnt;
paramSet.cCnt = ccnt;
/* For AB-synchronized transfers, BCNTRLD is not used. */
paramSet.bCntReload = BRCnt;
paramSet.linkAddr = 0xFFFFu;
/* Src & Dest are in INCR modes */
paramSet.opt &= 0xFFFFFFFCu;
/* Program the TCC */
paramSet.opt |= ((tcc1 << OPT_TCC_SHIFT) & OPT_TCC_MASK);
/* Enable Intermediate & Final transfer completion interrupt */
paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
if (syncType == EDMA3_DRV_SYNC_A)
{
paramSet.opt &= 0xFFFFFFFBu;
}
else
{
/* AB Sync Transfer Mode */
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
}
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM (hEdma, ch1Id, ¶mSet);
}
/*
* There is another way to program the PaRAM Set using specific APIs
* for different PaRAM set entries. It gives user more control and easier
* to use interface. User can use any of the methods.
* Below is the alternative way to program the PaRAM Set.
*/
/*
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
(unsigned int)(dstBuff1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
}
if (result == EDMA3_DRV_SOK)
{
if (syncType == EDMA3_DRV_SYNC_A)
{
result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
ccnt, BRCnt,
EDMA3_DRV_SYNC_A);
}
else
{
result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
ccnt, BRCnt,
EDMA3_DRV_SYNC_AB);
}
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setOptField (hEdma, ch1Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setOptField (hEdma, ch1Id,
EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
}
*/
/* Request any LINK channel and any TCC */
if (result == EDMA3_DRV_SOK)
{
/* Setup for Channel 2 */
ch2Id = EDMA3_DRV_LINK_CHANNEL;
tcc2 = EDMA3_DRV_TCC_ANY;
result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
(EDMA3_RM_EventQueue)0,
&callback1, NULL);
}
if (result == EDMA3_DRV_SOK)
{
/*
* Fill the PaRAM Set for the LINK channel
* with transfer specific information.
*/
paramSet.srcAddr = (unsigned int)(srcBuff2);
paramSet.destAddr = (unsigned int)(dstBuff2);
/**
* Be Careful !!!
* Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767
* Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767
*/
paramSet.srcBIdx = srcbidx;
paramSet.destBIdx = desbidx;
paramSet.srcCIdx = srccidx;
paramSet.destCIdx = descidx;
/**
* Be Careful !!!
* Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
* ACNT/BCNT/CCNT must be greater than or equal to 1.
* Maximum number of bytes in an array (ACNT) is 65535 bytes
* Maximum number of arrays in a frame (BCNT) is 65535
* Maximum number of frames in a block (CCNT) is 65535
*/
paramSet.aCnt = acnt;
paramSet.bCnt = bcnt;
paramSet.cCnt = ccnt;
/* For AB-synchronized transfers, BCNTRLD is not used. */
paramSet.bCntReload = BRCnt;
paramSet.linkAddr = 0xFFFFu;
/* Reset opt field first */
paramSet.opt = 0x0u;
/* Src & Dest are in INCR modes */
paramSet.opt &= 0xFFFFFFFCu;
/* Enable Intermediate & Final transfer completion interrupt */
paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
if (syncType == EDMA3_DRV_SYNC_A)
{
paramSet.opt &= 0xFFFFFFFBu;
}
else
{
/* AB Sync Transfer Mode */
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
}
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM(hEdma, ch2Id, ¶mSet);
}
/*
* There is another way to program the PaRAM Set using specific APIs
* for different PaRAM set entries. It gives user more control and easier
* to use interface. User can use any of the methods.
* Below is the alternative way to program the PaRAM Set.
*/
/*
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setDestParams (hEdma, ch2Id,
(unsigned int)(dstBuff2),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
}
if (result == EDMA3_DRV_SOK)
{
if (syncType == EDMA3_DRV_SYNC_A)
{
result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
ccnt,
BRCnt,EDMA3_DRV_SYNC_A);
}
else
{
result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
ccnt,
BRCnt,EDMA3_DRV_SYNC_AB);
}
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setOptField (hEdma, ch2Id,
EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
}
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_setOptField (hEdma, ch2Id,
EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
}
*/
/* Link both the channels. */
if (result == EDMA3_DRV_SOK)
{
result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
}
/*
* Since the transfer is going to happen in Manual mode of EDMA3
* operation, we have to 'Enable the Transfer' multiple times.
* Number of times depends upon the Mode (A/AB Sync)
* and the different counts.
*/
if (result == EDMA3_DRV_SOK)
{
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
{
numenabled = bcnt * ccnt;
}
else
{
/* AB Sync Transfer Mode */
numenabled = ccnt;
}
for (i = 0; i < numenabled; i++)
{
irqRaised1 = 0;
/*
* Now enable the transfer for Master channel as many times
* as calculated above.
*/
result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
{
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");
#endif /* EDMA3_DRV_DEBUG */
break;
}
while (irqRaised1 == 0)
{
/* Wait for the Completion ISR on Master Channel. */
printf ("waiting for interrupt...\n");
}
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
{
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");
#endif /* EDMA3_DRV_DEBUG */
/* Clear the error bits first */
result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);
break;
}
}
}
/**
* Now the transfer on Master channel is finished.
* Trigger next (LINK) param.
*/
if (EDMA3_DRV_SOK == result)
{
for (i = 0; i < numenabled; i++)
{
irqRaised1 = 0;
/*
* Enable the transfer for LINK channel as many times
* as calculated above.
*/
result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
{
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");
#endif /* EDMA3_DRV_DEBUG */
break;
}
while (irqRaised1 == 0)
{
/* Wait for the Completion ISR on the Link Channel. */
printf ("waiting for interrupt...\n");
}
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
{
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");
#endif /* EDMA3_DRV_DEBUG */
/* Clear the error bits first */
result = EDMA3_DRV_clearErrorBits (hEdma, ch2Id);
break;
}
}
}
/* Match the Source and Destination Buffers. */
if (EDMA3_DRV_SOK == result)
{
for (i = 0; i < (acnt*bcnt*ccnt); i++)
{
if (srcBuff1[i] != dstBuff1[i])
{
Istestpassed1 = 0u;
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \
"matching FAILED at i = %d " \
"(srcBuff1 -> dstBuff1)\r\n", i);
#endif /* EDMA3_DRV_DEBUG */
break;
}
}
if (i == (acnt*bcnt*ccnt))
{
Istestpassed1 = 1u;
}
for (i = 0; i < (acnt*bcnt*ccnt); i++)
{
if (srcBuff2[i] != dstBuff2[i])
{
Istestpassed2 = 0;
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \
"matching FAILED at i = %d " \
"(srcBuff2 -> dstBuff2)\r\n", i);
#endif /* EDMA3_DRV_DEBUG */
break;
}
}
if (i == (acnt*bcnt*ccnt))
{
Istestpassed2 = 1u;
}
/* Free the previously allocated channels. */
result = EDMA3_DRV_freeChannel (hEdma, ch1Id);
if (result != EDMA3_DRV_SOK)
{
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: EDMA3_DRV_freeChannel() " \
"for ch1 FAILED, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
}
else
{
result = EDMA3_DRV_freeChannel (hEdma, ch2Id);
if (result != EDMA3_DRV_SOK)
{
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: " \
"EDMA3_DRV_freeChannel() for ch 2 FAILED, " \
"error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
}
}
}
if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
{
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link PASSED\r\n");
#endif /* EDMA3_DRV_DEBUG */
}
else
{
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link FAILED\r\n");
#endif /* EDMA3_DRV_DEBUG */
result = ((EDMA3_DRV_SOK == result) ?
EDMA3_DATA_MISMATCH_ERROR : result);
}
return result;
}
// **************************************************************************************
EDMA3_DRV_Result edmaInitiateXferDoubleChain(const void *dst, const void *src, const int aCnt,
const int bCnt, const int cCnt, const int srcBIdx,
const int destBIdx, const int srcCIdx,
const int destCIdx, const int chCnt)
{
EDMA3_DRV_PaRAMRegs paramSet, *gParamSet;
uint32_t addr;
EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
signed char *srcBuf, *dstBuf;
volatile int coreCnt = determineProcId();
int bIndex; //, cIndex;
if((chCnt<0) || (chCnt>2) || ((chCnt&1) != 0))
{
System_printf("DMA channel (%d) not valid", chCnt);
System_abort("\n");
}
if(bCnt * cCnt > MAX_PARAMS-1)
{
System_printf("Can't handle bCnt(%d)*cCnt(%); max allowed is %d", bCnt, cCnt, MAX_PARAMS-1);
System_abort("\n");
}
srcBuf = (signed char*) getGlobalAddr((signed char *) src);
dstBuf = (signed char*) getGlobalAddr((signed char *) dst);
// set paramSet
paramSet.srcAddr = (unsigned int) srcBuf;
paramSet.destAddr = (unsigned int) dstBuf;
paramSet.aCnt = aCnt;
paramSet.bCnt = 1;
paramSet.cCnt = 1;
paramSet.srcBIdx = 0;
paramSet.destBIdx = 0;
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
paramSet.bCntReload = 0;
paramSet.linkAddr = 0xFFFFu;
paramSet.opt = 0x00000000u;
// enable final TCC chaining; only one transfer
paramSet.opt |= (1 << OPT_TCCHEN_SHIFT);
// set TCC to chained channel
paramSet.opt |= ((gEdmaXfer[coreCnt][chCnt+1].tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);
gParamSet = &globalParamSet[(coreCnt*(EDMA_CHANNELS>>1)+(chCnt>>1))*MAX_PARAMS];
// now write the paramsets to be used by the first of the doubly chained channels
for(bIndex = 0; bIndex <= bCnt; bIndex++)
{
// table of paramSet
gParamSet[bIndex] = paramSet;
// update src and dst address;
paramSet.srcAddr += srcBIdx;
paramSet.destAddr += destBIdx;
if(bIndex == (bCnt-1)) // last in the set
{
// set to be a dummy transfer
paramSet.aCnt = 1;
paramSet.bCnt = 0;
paramSet.cCnt = 0;
// disable chaining
paramSet.opt &= ~(1 << OPT_TCCHEN_SHIFT);
}
}
// ensure gParamSet is written to cache
Cache_wbInv(gParamSet, (bCnt+1)*sizeof(EDMA3_DRV_PaRAMRegs), Cache_Type_ALLD, 1);
// set paramSet; src is global param set; dst is chained PARAMset;
// src increment is size of PARAMset and dst address is always the same
paramSet.srcAddr = (uint32_t) getGlobalAddr((signed char *) &gParamSet[0]);
EDMA3_DRV_getPaRAMPhyAddr(gHEdma[coreCnt/4], gEdmaXfer[coreCnt][chCnt].chId, &addr);
paramSet.destAddr = (uint32_t) getGlobalAddr((signed char *) addr);
paramSet.aCnt = sizeof(EDMA3_DRV_PaRAMRegs);
paramSet.bCnt = bCnt+1;
paramSet.cCnt = 1;
paramSet.srcBIdx = sizeof(EDMA3_DRV_PaRAMRegs);
paramSet.destBIdx = 0;
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
paramSet.bCntReload = 0;
paramSet.linkAddr = 0xFFFFu;
paramSet.opt = 0x00000000u;
// both intermediate and final chaining enabled
paramSet.opt |= (1 << OPT_TCCHEN_SHIFT);
paramSet.opt |= (1 << OPT_ITCCHEN_SHIFT);
// final interrupt enabled
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
// set TCC to chained channel
paramSet.opt |= ((gEdmaXfer[coreCnt][chCnt].tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);
/* Now, write the PaRAM Set to the second of the doubly chained channels */
edmaResult = EDMA3_DRV_setPaRAM(gHEdma[coreCnt/4], gEdmaXfer[coreCnt][chCnt+1].chId, (EDMA3_DRV_PaRAMRegs *) ¶mSet);
// start transfer on the second of the doubly chained channels
if(edmaResult == EDMA3_DRV_SOK)
{
edmaResult = EDMA3_DRV_enableTransfer (gHEdma[coreCnt/4],
gEdmaXfer[coreCnt][chCnt+1].chId,
EDMA3_DRV_TRIG_MODE_MANUAL);
}
return(edmaResult);
} // edmaInitiateXferDoubleChain
