static bool sam3x_cmd_gpnvm_get(target *t) { uint32_t base = sam3x_flash_base(t); sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_GGPB, 0); tc_printf(t, "GPNVM: 0x%08X\n", target_mem_read32(t, EEFC_FRR(base))); return true; }
//----------------------------------------------------------------------------- static void target_select(target_options_t *options) { uint32_t chip_id, chip_exid; // Set boot mode GPNVM bit as a workaraound dap_write_word(EEFC_FCR(0), CMD_SGPB | (1 << 8)); // Stop the core dap_write_word(DHCSR, 0xa05f0003); dap_write_word(DEMCR, 0x00000001); dap_write_word(AIRCR, 0x05fa0004); chip_id = dap_read_word(CHIPID_CIDR); chip_exid = dap_read_word(CHIPID_EXID); for (device_t *device = devices; device->chip_id > 0; device++) { if (device->chip_id == chip_id && device->chip_exid == chip_exid) { uint32_t fl_id, fl_size, fl_page_size, fl_nb_palne, fl_nb_lock; verbose("Target: %s\n", device->name); for (uint32_t plane = 0; plane < device->n_planes; plane++) { dap_write_word(EEFC_FCR(plane), CMD_GETD); while (0 == (dap_read_word(EEFC_FSR(plane)) & FSR_FRDY)); fl_id = dap_read_word(EEFC_FRR(plane)); check(fl_id, "Cannot read flash descriptor, check Erase pin state"); fl_size = dap_read_word(EEFC_FRR(plane)); check(fl_size == device->flash_size, "Invalid reported Flash size (%d)", fl_size); fl_page_size = dap_read_word(EEFC_FRR(plane)); check(fl_page_size == device->page_size, "Invalid reported page size (%d)", fl_page_size); fl_nb_palne = dap_read_word(EEFC_FRR(plane)); for (uint32_t i = 0; i < fl_nb_palne; i++) dap_read_word(EEFC_FRR(plane)); fl_nb_lock = dap_read_word(EEFC_FRR(plane)); for (uint32_t i = 0; i < fl_nb_lock; i++) dap_read_word(EEFC_FRR(plane)); } target_device = *device; target_options = *options; target_check_options(&target_options, device->flash_size * target_device.n_planes, device->page_size * PAGES_IN_ERASE_BLOCK); return; } } error_exit("unknown target device (CHIP_ID = 0x%08x)", chip_id); }