void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// adjust the CCU delaye for EMI (default to zero)
//LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16));
// Move all clock delays together
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY)
| (CLK0_DELAY << 4)
| (CLK0_DELAY << 8)
| (CLK0_DELAY << 12));
/* Initialize EMC to interface with SDRAM */
LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */
LPC_EMC->CONFIG = 0;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14));
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
// LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
// LPC_EMC->DYNAMICRAS = 3;
// LPC_EMC->DYNAMICSREX = 5;
// LPC_EMC->DYNAMICAPR = 0;
// LPC_EMC->DYNAMICDAL = 4;
// LPC_EMC->DYNAMICWR = 1;
// LPC_EMC->DYNAMICRC = 5;
// LPC_EMC->DYNAMICRFC = 5;
// LPC_EMC->DYNAMICXSR = 5;
// LPC_EMC->DYNAMICRRD = 1;
// LPC_EMC->DYNAMICMRD = 1;
LPC_EMC->DYNAMICRP = 2; // calculated from xls sheet for 120 MHz
LPC_EMC->DYNAMICRAS = 5;
LPC_EMC->DYNAMICSREX = 8;
LPC_EMC->DYNAMICAPR = 1;
LPC_EMC->DYNAMICDAL = 5;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 8;
LPC_EMC->DYNAMICRFC = 8;
LPC_EMC->DYNAMICXSR = 8;
LPC_EMC->DYNAMICRRD = 1;
LPC_EMC->DYNAMICMRD = 1;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
emc_WaitUS(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
emc_WaitUS(100);
// LPC_EMC->DYNAMICREFRESH = 50;
LPC_EMC->DYNAMICREFRESH = 118;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// if(u32DataBus == 0)
// {
// /* burst size 8 */
// *((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1))));
// }
// else
// {
// /* burst size 4 */
// *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2))));
// }
if(u32DataBus == 0) // burst size 8, CAS3
{
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (3UL << 4)) << (u32ColAddrBits + 2 + 1))));
}
else // burst size 4, CAS3
{
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (3UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
}
/****************************************************************************************
* Configure the EMI for the SDRAM
*
* - on the Hitex board (IS42S16400D-7TL)
* - on the NXP validation board (MT48LC4M32B2)
*
****************************************************************************************/
void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// calculate a 1 usec delay base
delayBase1us = M4Frequency / DELAY_1usFreq;
// eventually adjust the CCU delays for EMI (default to zero)
initEmiDelays();
// Initialize EMC to interface with SDRAM. The EMC needs to run for this.
LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller
LPC_EMC->CONFIG = 0;
#if (PLATFORM == HITEX_A2_BOARD)
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0.
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.
LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period
LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period
LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time
LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time
LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.
LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time
LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period
LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period
LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time
LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency
LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
vDelay(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation
vDelay(100);
LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// Write configuration data to SDRAM device
if(u32DataBus == 0) { // 16-bit data bus, the EMC enforces a burst size 8
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
} else { // burst size 4 (which is not an option for 16-bit data bus anyway)
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
#endif // HITEX_BOARD
#if (PLATFORM == NXP_VALIDATION_BOARD)
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8);
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
LPC_EMC->DYNAMICRAS = 2;
LPC_EMC->DYNAMICSREX = 5;
LPC_EMC->DYNAMICAPR = 0;
LPC_EMC->DYNAMICDAL = 4;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 5;
LPC_EMC->DYNAMICRFC = 5;
LPC_EMC->DYNAMICXSR = 5;
LPC_EMC->DYNAMICRRD = 0;
LPC_EMC->DYNAMICMRD = 0;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
vDelay(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
vDelay(100);
LPC_EMC->DYNAMICREFRESH = 83;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// Write configuration data to SDRAM device
if(u32DataBus == 0) { // burst size 8
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
} else { // burst size 4
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
#endif // Validation board
LPC_EMC->DYNAMICCONTROL = 0;
LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers
}