/* this function initializes the platform with system level settings */
void platformInit(void) {
SystemInit();
/* checks for presence of an FPU unit */
fpuInit();
clockInit();
vIOInit();
#if (USE_EXT_STATIC_MEM == YES) || (USE_EXT_DYNAMIC_MEM == YES)
EMC_Init();
#endif
#if (USE_EXT_FLASH == YES)
// relocate vector table to internal ram
// updates also VTOR
relocIrqTable();
#endif
}
/* Initialize the external memory. */
void BOARD_InitSDRAM(void)
{
emc_basic_config_t basicConfig;
emc_dynamic_timing_config_t dynTiming;
emc_dynamic_chip_config_t dynChipConfig;
/* Basic configuration. */
basicConfig.endian = kEMC_LittleEndian;
basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
/* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
* If you change the divide to 0 and EMC clock is larger than 100M
* please take refer to emc.dox to adjust EMC clock delay.
*/
basicConfig.emcClkDiv = 1;
/* Dynamic memory timing configuration. */
dynTiming.readConfig = kEMC_Cmddelay;
dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
dynTiming.tRp_Ns = SDRAM_TRP_NS;
dynTiming.tRas_Ns = SDRAM_TRAS_NS;
dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
dynTiming.tApr_Ns = SDRAM_TAPR_NS;
dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */
dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
dynTiming.tRc_Ns = SDRAM_TRC_NS;
dynTiming.tRfc_Ns = SDRAM_RFC_NS;
dynTiming.tXsr_Ns = SDRAM_XSR_NS;
dynTiming.tRrd_Ns = SDRAM_RRD_NS;
dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
/* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
dynChipConfig.chipIndex = 0;
dynChipConfig.dynamicDevice = kEMC_Sdram;
dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
/* EMC Basic configuration. */
EMC_Init(EMC, &basicConfig);
/* EMC Dynamc memory configuration. */
EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
}
/*******************************************************************************************************************************
* Function Name: vd_g_IoSdramInitTask
* Called By: vd_g_IoMgrInitTask
* Timing: Initialization
* Description: Task to initialize IO
*
*******************************************************************************************************************************/
void vd_g_IoSdramInitTask(void)
{
uint32_t Temp;
uint32_t u2_t_idx;
uint32_t u4_t_idx;
#ifdef WRITE_16
volatile uint16_t *short_wr_ptr;
#else
volatile uint32_t *short_wr_ptr;
#endif
/* Initialize EMC */
EMC_Init();
//Configure memory layout, but MUST DISABLE BUFFERs during configuration
LPC_EMC->DynamicConfig0 = (U4)SDRAM_MEM_CONFIG_VAL; /* 16Mbit, 1Mx16, 2 banks, row=11, column=8 */
/*Configure timing for ISSI SDRAM IC42S16100E */
//Timing for 80MHz Bus
LPC_EMC->DynamicRasCas0 = (U4)DYNAMIC_RAS_CAS; /* Dynamic Ras Cas Latency Register */
LPC_EMC->DynamicReadConfig = (U4)DYNAMIC_READ_CONFIG; /* Dynamic Read Config Register */
LPC_EMC->DynamicRP = (U4)DYNAMIC_TRP_CONFIG; /* Dynamic tRP Config Register */
LPC_EMC->DynamicRAS = (U4)DYNAMIC_TRAS_CONFIG; /* Dynamic tRAS Config Register */
LPC_EMC->DynamicSREX = (U4)DYNAMIC_TSREX_CONFIG; /* Dynamic tSREX Config Register */
LPC_EMC->DynamicAPR = (U4)DYNAMIC_TAPR_CONFIG; /* Dynamic tAPR Config Register */
LPC_EMC->DynamicDAL = (U4)DYNAMIC_TDAL_CONFIG; /* Dynamic tDAL Config Register */
LPC_EMC->DynamicWR = (U4)DYNAMIC_TWR_CONFIG; /* Dynamic tWR Config Register */
LPC_EMC->DynamicRC = (U4)DYNAMIC_TRC_CONFIG; /* Dynamic tRC Config Register */
LPC_EMC->DynamicRFC = (U4)DYNAMIC_TRFC_CONFIG; /* Dynamic tRFC Config Register */
LPC_EMC->DynamicXSR = (U4)DYNAMIC_TXSR_CONFIG; /* Dynamic tXSR Config Register */
LPC_EMC->DynamicRRD = (U4)DYNAMIC_TRRD_CONFIG; /* Dynamic tRRD Config Register */
LPC_EMC->DynamicMRD = (U4)DYNAMIC_TMRD_CONFIG; /* Dynamic tMRD Config Register */
//for(u4_t_idx = (U4)0; u4_t_idx < (U4)0x1F40; u4_t_idx++); /* wait ~100usec */
//LPC_EMC->DynamicControl = (U4)(SDRAM_NOP_COMMAND | SDRAM_CLK_CKE_HIGH); /* Issue NOP command */
for(u4_t_idx = (U4)0; u4_t_idx < (U4)0x12BF; u4_t_idx++); /* wait ~200usec */
LPC_EMC->DynamicControl = (U4)(SDRAM_PALL_COMMAND | SDRAM_CLK_CKE_HIGH); /* Issue PALL command */
LPC_EMC->DynamicRefresh = 0x00000001; /* ( n * 16 ) -> 16 clock cycles */
for(u4_t_idx = (U4)0; u4_t_idx < (U4)0x80; u4_t_idx++); /* wait 128 AHB clock cycles */
LPC_EMC->DynamicRefresh = (U4)DYNAMIC_REFRESH_RATE; /* 1248 clock cycles -> 15.6uS at 80MHz <= 15.625uS ( 32ms / 2048 row ) */
for(u4_t_idx = (U4)0; u4_t_idx < 0x80; u4_t_idx++); /* wait 128 AHB clock cycles */
LPC_EMC->DynamicControl = (U4)(SDRAM_MODE_COMMAND | SDRAM_CLK_CKE_HIGH); /* Issue MODE command */
Temp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (U4)SDRAM_MODE_COMMAND_VAL)); /* Set MODE on SDRAM chip with READ cycle */
for(u4_t_idx = (U4)0; u4_t_idx < 0x80; u4_t_idx++); /* wait 128 AHB clock cycles */
LPC_EMC->DynamicControl = (U4)SDRAM_NORMAL_COMMAND; /* Issue NORMAL command */
LPC_EMC->DynamicConfig0 |= (U4)SDRAM_BUFFER_ENABLE; /* Re-Enable Buffers */
for(u4_t_idx = (U4)0; u4_t_idx < 0x80; u4_t_idx++); /* Wait 128 AHB clock cycles */
/**********************/
/* Clear RAM Location */
/**********************/
#ifdef WRITE_16
short_wr_ptr = (uint16_t *)SDRAM_BASE_ADDR; /* Set Pointer to beginning of RAM */
for (u4_t_idx = (U4)0; u4_t_idx < (SDRAM_SIZE_U2/2); u4_t_idx++ )
{
*short_wr_ptr++ = (U2)GREEN;
*short_wr_ptr++ = (U2)GREEN;
}
#else
short_wr_ptr = (uint32_t *)SDRAM_BASE_ADDR;
for (u4_t_idx = (U4)0; u4_t_idx < (SDRAM_SIZE_U4/4); u4_t_idx++ )
{
*short_wr_ptr++ = (U4)0x00000000;
}
/*for (u4_t_idx = (U4)0; u4_t_idx < ((SDRAM_SIZE_U4/8)); u4_t_idx++ )
{
*short_wr_ptr++ = (U4)0xFFFFFFFF;
}
for (u4_t_idx = (U4)0; u4_t_idx < ((SDRAM_SIZE_U4/16)); u4_t_idx++ )
{
*short_wr_ptr++ = (U4)0xFFFFFFFF;
}
for (u4_t_idx = (U4)0; u4_t_idx < ((SDRAM_SIZE_U4/16)); u4_t_idx++ )
{
*short_wr_ptr++ = (U4)0xFFFFFFFF;
}*/
#endif
}
