/*
* We patch this function into tnl->Driver.Render.Start.
* It's called when we start rendering a vertex buffer.
*/
static void
_swsetup_RenderStart( GLcontext *ctx )
{
SScontext *swsetup = SWSETUP_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
GLuint new_state = swsetup->NewState;
if (new_state & _SWSETUP_NEW_RENDERINDEX) {
_swsetup_choose_trifuncs( ctx );
}
swsetup->NewState = 0;
_swrast_render_start( ctx );
/* Important:
*/
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
if (tnl->render_inputs != swsetup->last_index) {
GLuint index = tnl->render_inputs;
struct tnl_attr_map map[_TNL_ATTRIB_MAX];
int i, e = 0;
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, win );
if (index & _TNL_BIT_COLOR0)
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4CHAN_4F_RGBA, color );
if (index & _TNL_BIT_COLOR1)
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4CHAN_4F_RGBA, specular);
if (index & _TNL_BIT_FOG)
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F, fog);
if (index & _TNL_BITS_TEX_ANY) {
for (i = 0; i < MAX_TEXTURE_COORD_UNITS; i++) {
if (index & _TNL_BIT_TEX(i)) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_4F, texcoord[i] );
}
}
}
if (index & _TNL_BIT_INDEX)
EMIT_ATTR( _TNL_ATTRIB_INDEX, EMIT_1F, index );
if (index & _TNL_BIT_POINTSIZE)
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, pointSize );
_tnl_install_attrs( ctx, map, e,
ctx->Viewport._WindowMap.m,
sizeof(SWvertex) );
swsetup->last_index = index;
}
}
/**
* Tell the tnl module how to build SWvertex objects for swrast.
* We'll build the map[] array with that info and pass it to
* _tnl_install_attrs().
*/
static void
setup_vertex_format(struct gl_context *ctx)
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
SScontext *swsetup = SWSETUP_CONTEXT(ctx);
GLboolean intColors = ctx->RenderMode == GL_RENDER
&& CHAN_TYPE != GL_FLOAT;
if (intColors != swsetup->intColors ||
tnl->render_inputs_bitset != swsetup->last_index_bitset) {
GLbitfield64 index_bitset = tnl->render_inputs_bitset;
struct tnl_attr_map map[_TNL_ATTRIB_MAX];
unsigned e = 0;
swsetup->intColors = intColors;
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, attrib[FRAG_ATTRIB_WPOS] );
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR)) {
if (swsetup->intColors)
EMIT_ATTR( _TNL_ATTRIB_COLOR, EMIT_4CHAN_4F_RGBA, color );
else
EMIT_ATTR( _TNL_ATTRIB_COLOR, EMIT_4F, attrib[FRAG_ATTRIB_COL]);
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F, attrib[FRAG_ATTRIB_FOGC]);
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX)) {
EMIT_ATTR( _TNL_ATTRIB_TEX, EMIT_4F,
attrib[FRAG_ATTRIB_TEX] );
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE))
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, pointSize );
_tnl_install_attrs( ctx, map, e,
ctx->Viewport._WindowMap.m,
sizeof(SWvertex) );
swsetup->last_index_bitset = index_bitset;
}
}
static void
i830_render_start(struct intel_context *intel)
{
GLcontext *ctx = &intel->ctx;
struct i830_context *i830 = i830_context(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
DECLARE_RENDERINPUTS(index_bitset);
GLuint v0 = _3DSTATE_VFT0_CMD;
GLuint v2 = _3DSTATE_VFT1_CMD;
GLuint mcsb1 = 0;
RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
/* Important:
*/
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
intel->vertex_attr_count = 0;
/* EMIT_ATTR's must be in order as they tell t_vertex.c how to
* build up a hardware vertex.
*/
if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
intel->coloroffset = 4;
}
else {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
intel->coloroffset = 3;
}
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
}
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
intel->specoffset = 0;
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
intel->specoffset = intel->coloroffset + 1;
EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
}
else
EMIT_PAD(3);
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
else
EMIT_PAD(1);
}
if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
int i, count = 0;
for (i = 0; i < I830_TEX_UNITS; i++) {
if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
GLuint sz = VB->TexCoordPtr[i]->size;
GLuint emit;
GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
~TEXCOORDTYPE_MASK);
switch (sz) {
case 1:
case 2:
emit = EMIT_2F;
sz = 2;
mcs |= TEXCOORDTYPE_CARTESIAN;
break;
case 3:
emit = EMIT_3F;
sz = 3;
mcs |= TEXCOORDTYPE_VECTOR;
break;
case 4:
emit = EMIT_3F_XYW;
sz = 3;
mcs |= TEXCOORDTYPE_HOMOGENEOUS;
break;
default:
continue;
};
EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
mcsb1 |= (count + 8) << (i * 4);
if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
}
count++;
}
}
v0 |= VFT0_TEX_COUNT(count);
}
/* Only need to change the vertex emit code if there has been a
* statechange to a new hardware vertex format:
*/
if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
!RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
int k;
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
/* Must do this *after* statechange, so as not to affect
* buffered vertices reliant on the old state:
*/
intel->vertex_size =
_tnl_install_attrs(ctx,
intel->vertex_attrs,
intel->vertex_attr_count,
intel->ViewportMatrix.m, 0);
intel->vertex_size >>= 2;
i830->state.Ctx[I830_CTXREG_VF] = v0;
i830->state.Ctx[I830_CTXREG_VF2] = v2;
i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
k = i830_check_vertex_size(intel, intel->vertex_size);
assert(k);
}
/**
* Tell the tnl module how to build SWvertex objects for swrast.
* We'll build the map[] array with that info and pass it to
* _tnl_install_attrs().
*/
static void
setup_vertex_format(struct gl_context *ctx)
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
SScontext *swsetup = SWSETUP_CONTEXT(ctx);
GLboolean intColors = !ctx->FragmentProgram._Current
&& !ctx->ATIFragmentShader._Enabled
&& ctx->RenderMode == GL_RENDER
&& CHAN_TYPE != GL_FLOAT;
if (intColors != swsetup->intColors ||
tnl->render_inputs_bitset != swsetup->last_index_bitset) {
GLbitfield64 index_bitset = tnl->render_inputs_bitset;
struct tnl_attr_map map[_TNL_ATTRIB_MAX];
unsigned int i, e = 0;
swsetup->intColors = intColors;
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, attrib[VARYING_SLOT_POS] );
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR0)) {
if (swsetup->intColors)
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4CHAN_4F_RGBA, color );
else
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4F, attrib[VARYING_SLOT_COL0]);
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4F, attrib[VARYING_SLOT_COL1]);
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
const GLint emit = ctx->FragmentProgram._Current ? EMIT_4F : EMIT_1F;
EMIT_ATTR( _TNL_ATTRIB_FOG, emit, attrib[VARYING_SLOT_FOGC]);
}
if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))
{
for (i = 0; i < MAX_TEXTURE_COORD_UNITS; i++) {
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
EMIT_ATTR( _TNL_ATTRIB_TEX(i), EMIT_4F,
attrib[VARYING_SLOT_TEX0 + i] );
}
}
}
/* shader varying vars */
if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_GENERIC0, _TNL_NUM_GENERIC)) {
for (i = 0; i < ctx->Const.MaxVarying; i++) {
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_GENERIC(i))) {
EMIT_ATTR( _TNL_ATTRIB_GENERIC(i), VARYING_EMIT_STYLE,
attrib[VARYING_SLOT_VAR0 + i] );
}
}
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE))
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, pointSize );
_tnl_install_attrs( ctx, map, e,
ctx->Viewport._WindowMap.m,
sizeof(SWvertex) );
swsetup->last_index_bitset = index_bitset;
}
}
void
i915ValidateFragmentProgram(struct i915_context *i915)
{
GLcontext *ctx = &i915->intel.ctx;
struct intel_context *intel = intel_context(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
struct i915_fragment_program *p =
(struct i915_fragment_program *) ctx->FragmentProgram._Current;
const GLuint inputsRead = p->FragProg.Base.InputsRead;
GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
GLuint s2 = S2_TEXCOORD_NONE;
int i, offset = 0;
if (i915->current_program != p) {
if (i915->current_program) {
i915->current_program->on_hardware = 0;
i915->current_program->params_uptodate = 0;
}
i915->current_program = p;
}
/* Important:
*/
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
if (!p->translated)
translate_program(p);
intel->vertex_attr_count = 0;
intel->wpos_offset = 0;
intel->wpos_size = 0;
intel->coloroffset = 0;
intel->specoffset = 0;
if (inputsRead & FRAG_BITS_TEX_ANY) {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16);
}
else {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, S4_VFMT_XYZ, 12);
}
if (inputsRead & FRAG_BIT_COL0) {
intel->coloroffset = offset / 4;
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
}
if ((inputsRead & (FRAG_BIT_COL1 | FRAG_BIT_FOGC)) ||
i915->vertex_fog != I915_FOG_NONE) {
if (inputsRead & FRAG_BIT_COL1) {
intel->specoffset = offset / 4;
EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3);
}
else
EMIT_PAD(3);
if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE)
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1);
else
EMIT_PAD(1);
}
/* XXX this was disabled, but enabling this code helped fix the Glean
* tfragprog1 fog tests.
*/
#if 1
if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE) {
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4);
}
#endif
for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
if (inputsRead & FRAG_BIT_TEX(i)) {
int sz = VB->TexCoordPtr[i]->size;
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(sz));
EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, EMIT_SZ(sz), 0, sz * 4);
}
else if (i == p->wpos_tex) {
/* If WPOS is required, duplicate the XYZ position data in an
* unused texture coordinate:
*/
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(3));
intel->wpos_offset = offset;
intel->wpos_size = 3 * sizeof(GLuint);
EMIT_PAD(intel->wpos_size);
}
}
if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] ||
s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
int k;
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
/* Must do this *after* statechange, so as not to affect
* buffered vertices reliant on the old state:
*/
intel->vertex_size = _tnl_install_attrs(&intel->ctx,
intel->vertex_attrs,
intel->vertex_attr_count,
intel->ViewportMatrix.m, 0);
intel->vertex_size >>= 2;
i915->state.Ctx[I915_CTXREG_LIS2] = s2;
i915->state.Ctx[I915_CTXREG_LIS4] = s4;
k = intel->vtbl.check_vertex_size(intel, intel->vertex_size);
assert(k);
}
void r300ChooseSwtclVertexFormat(GLcontext *ctx, GLuint *_InputsRead, GLuint *_OutputsWritten)
{
r300ContextPtr rmesa = R300_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
int first_free_tex = 0;
GLuint InputsRead = 0;
GLuint OutputsWritten = 0;
int num_attrs = 0;
GLuint fp_reads = rmesa->selected_fp->InputsRead;
struct vertex_attribute *attrs = rmesa->vbuf.attribs;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0;
rmesa->radeon.swtcl.vertex_attr_count = 0;
if (RADEON_DEBUG & RADEON_VERTS)
fprintf(stderr, "%s\n", __func__);
/* We always want non Ndc coords format */
VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
/* Always write position vector */
InputsRead |= 1 << VERT_ATTRIB_POS;
OutputsWritten |= 1 << VERT_RESULT_HPOS;
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F );
ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0);
rmesa->swtcl.coloroffset = 4;
if (fp_reads & FRAG_BIT_COL0) {
InputsRead |= 1 << VERT_ATTRIB_COLOR0;
OutputsWritten |= 1 << VERT_RESULT_COL0;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1);
#endif
}
if (fp_reads & FRAG_BIT_COL1) {
GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
InputsRead |= 1 << VERT_ATTRIB_COLOR1;
OutputsWritten |= 1 << VERT_RESULT_COL1;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1);
#endif
rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1;
}
if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
VB->AttribPtr[VERT_ATTRIB_GENERIC0] = VB->ColorPtr[1];
OutputsWritten |= 1 << VERT_RESULT_BFC0;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1);
#endif
if (fp_reads & FRAG_BIT_COL1) {
VB->AttribPtr[VERT_ATTRIB_GENERIC1] = VB->SecondaryColorPtr[1];
GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
OutputsWritten |= 1 << VERT_RESULT_BFC1;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1);
#endif
}
}
if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) {
GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO);
InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE;
OutputsWritten |= 1 << VERT_RESULT_PSIZ;
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F );
ADD_ATTR(VERT_ATTRIB_POINT_SIZE, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_POINT_SIZE, swiz, MASK_X, 0);
}
if (rmesa->selected_fp->wpos_attr != FRAG_ATTRIB_MAX) {
int tex_id = rmesa->selected_fp->wpos_attr - FRAG_ATTRIB_TEX0;
VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS];
VB->TexCoordPtr[tex_id] = VB->AttribPtr[VERT_ATTRIB_POS];
RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id);
}
if (rmesa->selected_fp->fog_attr != FRAG_ATTRIB_MAX) {
int tex_id = rmesa->selected_fp->fog_attr - FRAG_ATTRIB_TEX0;
VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG];
VB->TexCoordPtr[tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG];
RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id);
}
/**
* Sending only one texcoord component may lead to lock up,
* so for all textures always output 4 texcoord components to RS.
*/
{
int i;
GLuint swiz, format, hw_format;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (fp_reads & FRAG_BIT_TEX(i)) {
switch (VB->TexCoordPtr[i]->size) {
case 1:
format = EMIT_1F;
hw_format = R300_DATA_TYPE_FLOAT_1;
swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
break;
case 2:
format = EMIT_2F;
hw_format = R300_DATA_TYPE_FLOAT_2;
swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE);
break;
case 3:
format = EMIT_3F;
hw_format = R300_DATA_TYPE_FLOAT_3;
swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
break;
case 4:
format = EMIT_4F;
hw_format = R300_DATA_TYPE_FLOAT_4;
swiz = SWIZZLE_XYZW;
break;
default:
continue;
}
InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i);
OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i);
EMIT_ATTR(_TNL_ATTRIB_TEX(i), format);
ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0);
++first_free_tex;
}
}
}
if (first_free_tex >= ctx->Const.MaxTextureUnits) {
fprintf(stderr, "\tout of free texcoords to write fog coordinate\n");
_mesa_exit(-1);
}
R300_NEWPRIM(rmesa);
rmesa->vbuf.num_attribs = num_attrs;
*_InputsRead = InputsRead;
*_OutputsWritten = OutputsWritten;
RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset);
}
static void radeonSetVertexFormat( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
GLbitfield64 index_bitset = tnl->render_inputs_bitset;
int fmt_0 = 0;
int offset = 0;
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
}
else {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
}
assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
rmesa->radeon.swtcl.vertex_attr_count = 0;
/* EMIT_ATTR's must be in order as they tell t_vertex.c how to
* build up a hardware vertex.
*/
if ( !rmesa->swtcl.needproj ||
(index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
/* for projtex */
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
offset = 4;
}
else {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
offset = 3;
}
rmesa->swtcl.coloroffset = offset;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
RADEON_CP_VC_FRMT_PKCOLOR );
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
RADEON_CP_VC_FRMT_PKCOLOR );
#endif
offset += 1;
rmesa->swtcl.specoffset = 0;
if (index_bitset &
(BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
#if MESA_LITTLE_ENDIAN
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 3 );
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 1 );
}
#else
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 1 );
}
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 3 );
}
#endif
}
if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
int i;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
switch (sz) {
case 1:
case 2:
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
radeon_cp_vc_frmts[i][0] );
break;
case 3:
if (ctx->Texture.Unit[i]._Current &&
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
radeon_cp_vc_frmts[i][1] );
} else {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
radeon_cp_vc_frmts[i][0] );
}
break;
case 4:
if (ctx->Texture.Unit[i]._Current &&
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
radeon_cp_vc_frmts[i][1] );
} else {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
radeon_cp_vc_frmts[i][1] );
}
break;
default:
continue;
};
}
}
}
if (rmesa->radeon.tnl_index_bitset != index_bitset ||
fmt_0 != rmesa->swtcl.vertex_format) {
RADEON_NEWPRIM(rmesa);
rmesa->swtcl.vertex_format = fmt_0;
rmesa->radeon.swtcl.vertex_size =
_tnl_install_attrs( ctx,
rmesa->radeon.swtcl.vertex_attrs,
rmesa->radeon.swtcl.vertex_attr_count,
NULL, 0 );
rmesa->radeon.swtcl.vertex_size /= 4;
rmesa->radeon.tnl_index_bitset = index_bitset;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
"%s: vertex_size= %d floats\n", __func__, rmesa->radeon.swtcl.vertex_size);
}
}
static void viaChooseVertexState( struct gl_context *ctx )
{
struct via_context *vmesa = VIA_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
DECLARE_RENDERINPUTS(index_bitset);
GLuint regCmdB = HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Z;
GLuint setupIndex = 0;
RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
vmesa->vertex_attr_count = 0;
/* EMIT_ATTR's must be in order as they tell t_vertex.c how to
* build up a hardware vertex.
*/
if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) ||
RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VIA_EMIT_W, HC_HVPMSK_W );
vmesa->coloroffset = 4;
}
else {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, 0, 0 );
vmesa->coloroffset = 3;
}
/* t_context.c always includes a diffuse color */
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VIA_EMIT_RGBA,
HC_HVPMSK_Cd );
vmesa->specoffset = 0;
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
vmesa->specoffset = vmesa->coloroffset + 1;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VIA_EMIT_SPEC,
HC_HVPMSK_Cs );
}
else
EMIT_PAD( 3 );
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG ))
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, VIA_EMIT_FOG, HC_HVPMSK_Cs );
else
EMIT_PAD( 1 );
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX0 )) {
if (vmesa->ptexHack)
EMIT_ATTR( _TNL_ATTRIB_TEX0, EMIT_3F_XYW, VIA_EMIT_PTEX0,
(HC_HVPMSK_S | HC_HVPMSK_T) );
else
EMIT_ATTR( _TNL_ATTRIB_TEX0, EMIT_2F, VIA_EMIT_TEX0,
(HC_HVPMSK_S | HC_HVPMSK_T) );
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX1 )) {
EMIT_ATTR( _TNL_ATTRIB_TEX1, EMIT_2F, VIA_EMIT_TEX1,
(HC_HVPMSK_S | HC_HVPMSK_T) );
}
if (setupIndex != vmesa->setupIndex) {
vmesa->vertexSize = _tnl_install_attrs( ctx,
vmesa->vertex_attrs,
vmesa->vertex_attr_count,
vmesa->ViewportMatrix.m, 0 );
vmesa->vertexSize >>= 2;
vmesa->setupIndex = setupIndex;
vmesa->regCmdB &= ~HC_HVPMSK_MASK;
vmesa->regCmdB |= regCmdB;
if (vmesa->ptexHack)
vmesa->hwVertexSize = vmesa->vertexSize - 1;
else
vmesa->hwVertexSize = vmesa->vertexSize;
}
static void radeonSetVertexFormat( GLcontext *ctx )
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
DECLARE_RENDERINPUTS(index_bitset);
int fmt_0 = 0;
int offset = 0;
RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
}
else {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
}
assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
rmesa->swtcl.vertex_attr_count = 0;
/* EMIT_ATTR's must be in order as they tell t_vertex.c how to
* build up a hardware vertex.
*/
if ( !rmesa->swtcl.needproj ||
RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { /* for projtex */
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
offset = 4;
}
else {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
offset = 3;
}
rmesa->swtcl.coloroffset = offset;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
RADEON_CP_VC_FRMT_PKCOLOR );
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
RADEON_CP_VC_FRMT_PKCOLOR );
#endif
offset += 1;
rmesa->swtcl.specoffset = 0;
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
#if MESA_LITTLE_ENDIAN
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 3 );
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 1 );
}
#else
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 1 );
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
RADEON_CP_VC_FRMT_PKSPEC );
}
else {
EMIT_PAD( 3 );
}
#endif
}
if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
int i;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
GLuint sz = VB->TexCoordPtr[i]->size;
switch (sz) {
case 1:
case 2:
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
radeon_cp_vc_frmts[i][0] );
break;
case 3:
case 4:
if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
radeon_cp_vc_frmts[i][1] );
} else {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
radeon_cp_vc_frmts[i][1] );
}
break;
default:
continue;
};
}
}
}
if (!RENDERINPUTS_EQUAL( rmesa->tnl_index_bitset, index_bitset ) ||
fmt_0 != rmesa->swtcl.vertex_format) {
RADEON_NEWPRIM(rmesa);
rmesa->swtcl.vertex_format = fmt_0;
rmesa->swtcl.vertex_size =
_tnl_install_attrs( ctx,
rmesa->swtcl.vertex_attrs,
rmesa->swtcl.vertex_attr_count,
NULL, 0 );
rmesa->swtcl.vertex_size /= 4;
RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset );
if (RADEON_DEBUG & DEBUG_VERTS)
fprintf( stderr, "%s: vertex_size= %d floats\n",
__FUNCTION__, rmesa->swtcl.vertex_size);
}
}
static void sisRenderStart( struct gl_context *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
sisContextPtr smesa = SIS_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
DECLARE_RENDERINPUTS(index_bitset);
GLuint AGPParseSet = smesa->AGPParseSet;
GLboolean tex_fallback = GL_FALSE;
RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
if (ctx->DrawBuffer->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT &&
smesa->driDrawable->numClipRects != 0)
{
multipass_cliprect(ctx, 0);
if (smesa->driDrawable->numClipRects > 1)
tnl->Driver.Render.Multipass = multipass_cliprect;
else
tnl->Driver.Render.Multipass = NULL;
} else {
tnl->Driver.Render.Multipass = NULL;
}
/* Important:
*/
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
smesa->vertex_attr_count = 0;
/* EMIT_ATTR's must be in order as they tell t_vertex.c how to build up a
* hardware vertex.
*/
AGPParseSet &= ~(MASK_VertexDWSize | MASK_VertexDataFormat);
AGPParseSet |= SiS_PS_HAS_XYZ | SiS_PS_HAS_DIFFUSE;
if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT);
AGPParseSet |= SiS_PS_HAS_W;
smesa->coloroffset = 4;
} else {
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT);
smesa->coloroffset = 3;
}
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA);
smesa->specoffset = 0;
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
AGPParseSet |= SiS_PS_HAS_SPECULAR;
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR);
smesa->specoffset = smesa->coloroffset + 1;
} else {
EMIT_PAD(3);
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F);
} else {
EMIT_PAD(1);
}
}
/* projective textures are not supported by the hardware */
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX0 )) {
if (VB->AttribPtr[_TNL_ATTRIB_TEX0]->size > 2)
tex_fallback = GL_TRUE;
EMIT_ATTR(_TNL_ATTRIB_TEX0, EMIT_2F);
AGPParseSet |= SiS_PS_HAS_UV0;
}
/* Will only hit tex1 on SiS300 */
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX1 )) {
if (VB->AttribPtr[_TNL_ATTRIB_TEX1]->size > 2)
tex_fallback = GL_TRUE;
EMIT_ATTR(_TNL_ATTRIB_TEX1, EMIT_2F);
AGPParseSet |= SiS_PS_HAS_UV1;
}
FALLBACK(smesa, SIS_FALLBACK_TEXTURE, tex_fallback);
if (!RENDERINPUTS_EQUAL( smesa->last_tcl_state_bitset, index_bitset )) {
smesa->AGPParseSet = AGPParseSet;
smesa->vertex_size = _tnl_install_attrs( ctx, smesa->vertex_attrs,
smesa->vertex_attr_count, smesa->hw_viewport, 0 );
smesa->vertex_size >>= 2;
smesa->AGPParseSet |= smesa->vertex_size << 28;
}
static inline void nv10OutputVertexFormat(struct nouveau_context* nmesa)
{
GLcontext* ctx=nmesa->glCtx;
TNLcontext *tnl = TNL_CONTEXT(ctx);
DECLARE_RENDERINPUTS(index);
struct vertex_buffer *VB = &tnl->vb;
int attr_size[16];
int default_attr_size[8]={3,3,3,4,3,1,4,4};
int i;
int slots=0;
int total_size=0;
nmesa->vertex_attr_count = 0;
RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset);
/*
* Determine attribute sizes
*/
for(i=0;i<8;i++)
{
if (RENDERINPUTS_TEST(index, i))
attr_size[i]=default_attr_size[i];
else
attr_size[i]=0;
}
for(i=8;i<16;i++)
{
if (RENDERINPUTS_TEST(index, i))
attr_size[i]=VB->TexCoordPtr[i-8]->size;
else
attr_size[i]=0;
}
/*
* Tell t_vertex about the vertex format
*/
for(i=0;i<16;i++)
{
if (RENDERINPUTS_TEST(index, i))
{
slots=i+1;
switch(attr_size[i])
{
case 1:
EMIT_ATTR(i,EMIT_1F);
break;
case 2:
EMIT_ATTR(i,EMIT_2F);
break;
case 3:
EMIT_ATTR(i,EMIT_3F);
break;
case 4:
EMIT_ATTR(i,EMIT_4F);
break;
}
if (i==_TNL_ATTRIB_COLOR0)
nmesa->color_offset=total_size;
if (i==_TNL_ATTRIB_COLOR1)
nmesa->specular_offset=total_size;
total_size+=attr_size[i];
}
}
nmesa->vertex_size=_tnl_install_attrs( ctx,
nmesa->vertex_attrs,
nmesa->vertex_attr_count,
NULL, 0 );
assert(nmesa->vertex_size==total_size*4);
/*
* Tell the hardware about the vertex format
*/
if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) {
int size;
#define NV_VERTEX_ATTRIBUTE_TYPE_FLOAT 2
#define NV10_SET_VERTEX_ATTRIB(i,j) \
do { \
size = attr_size[j] << 4; \
size |= (attr_size[j]*4) << 8; \
size |= NV_VERTEX_ATTRIBUTE_TYPE_FLOAT; \
BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR(i),1); \
OUT_RING_CACHE(size); \
} while (0)
NV10_SET_VERTEX_ATTRIB(0, _TNL_ATTRIB_POS);
NV10_SET_VERTEX_ATTRIB(1, _TNL_ATTRIB_COLOR0);
NV10_SET_VERTEX_ATTRIB(2, _TNL_ATTRIB_COLOR1);
NV10_SET_VERTEX_ATTRIB(3, _TNL_ATTRIB_TEX0);
NV10_SET_VERTEX_ATTRIB(4, _TNL_ATTRIB_TEX1);
NV10_SET_VERTEX_ATTRIB(5, _TNL_ATTRIB_NORMAL);
NV10_SET_VERTEX_ATTRIB(6, _TNL_ATTRIB_WEIGHT);
NV10_SET_VERTEX_ATTRIB(7, _TNL_ATTRIB_FOG);
BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_VALIDATE,1);
OUT_RING_CACHE(0);
} else if (nmesa->screen->card->type==NV_20) {
for(i=0;i<16;i++)
{
int size=attr_size[i];
BEGIN_RING_CACHE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR(i),1);
OUT_RING_CACHE(NV_VERTEX_ATTRIBUTE_TYPE_FLOAT|(size*0x10));
}
} else {
BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DO_VERTICES, 1);
OUT_RING(0);
BEGIN_RING_CACHE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS,slots);
for(i=0;i<slots;i++)
{
int size=attr_size[i];
OUT_RING_CACHE(NV_VERTEX_ATTRIBUTE_TYPE_FLOAT|(size*0x10));
}
// FIXME this is probably not needed
BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0,1);
OUT_RING(0);
BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0,1);
OUT_RING(0);
BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0,1);
OUT_RING(0);
}
}
void i915ValidateTextureProgram( struct i915_context *i915 )
{
struct intel_context *intel = &i915->intel;
GLcontext *ctx = &intel->ctx;
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
GLuint index = tnl->render_inputs;
int i, offset;
GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
GLuint s2 = S2_TEXCOORD_NONE;
/* Important:
*/
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
intel->vertex_attr_count = 0;
intel->coloroffset = 0;
intel->specoffset = 0;
offset = 0;
if (i915->vertex_fog == I915_FOG_PIXEL) {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16 );
index &= ~_TNL_BIT_FOG;
}
else if (index & _TNL_BITS_TEX_ANY) {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16 );
}
else {
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, S4_VFMT_XYZ, 12 );
}
/* How undefined is undefined? */
if (index & _TNL_BIT_POINTSIZE) {
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, S4_VFMT_POINT_WIDTH, 4 );
}
intel->coloroffset = offset / 4;
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4 );
if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) {
if (index & _TNL_BIT_COLOR1) {
intel->specoffset = offset / 4;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3 );
} else
EMIT_PAD( 3 );
if (index & _TNL_BIT_FOG)
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1 );
else
EMIT_PAD( 1 );
}
if (index & _TNL_BITS_TEX_ANY) {
for (i = 0; i < 8; i++) {
if (index & _TNL_BIT_TEX(i)) {
int sz = VB->TexCoordPtr[i]->size;
s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(sz));
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_SZ(sz), 0, sz * 4 );
}
}
}
/* Only need to change the vertex emit code if there has been a
* statechange to a new hardware vertex format:
*/
if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] ||
s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
int k;
I915_STATECHANGE( i915, I915_UPLOAD_CTX );
i915->tex_program.translated = 0;
/* Must do this *after* statechange, so as not to affect
* buffered vertices reliant on the old state:
*/
intel->vertex_size = _tnl_install_attrs( ctx,
intel->vertex_attrs,
intel->vertex_attr_count,
intel->ViewportMatrix.m, 0 );
intel->vertex_size >>= 2;
i915->state.Ctx[I915_CTXREG_LIS2] = s2;
i915->state.Ctx[I915_CTXREG_LIS4] = s4;
k = intel->vtbl.check_vertex_size( intel, intel->vertex_size );
assert(k);
}
static void r128RenderStart( GLcontext *ctx )
{
r128ContextPtr rmesa = R128_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
DECLARE_RENDERINPUTS(index_bitset);
GLuint vc_frmt = 0;
GLboolean fallback_projtex = GL_FALSE;
GLuint offset = 0;
RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
/* Important: */
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
rmesa->vertex_attr_count = 0;
rmesa->specoffset = 0;
/* EMIT_ATTR's must be in order as they tell t_vertex.c how to
* build up a hardware vertex.
*/
if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ))
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, R128_CCE_VC_FRMT_RHW, 4 );
else
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, 0, 3 );
rmesa->coloroffset = offset;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA,
R128_CCE_VC_FRMT_DIFFUSE_ARGB, 4 );
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ARGB,
R128_CCE_VC_FRMT_DIFFUSE_ARGB, 4 );
#endif
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
#if MESA_LITTLE_ENDIAN
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
rmesa->specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
R128_CCE_VC_FRMT_SPEC_FRGB, 3 );
} else
EMIT_PAD( 3 );
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG ))
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, R128_CCE_VC_FRMT_SPEC_FRGB,
1 );
else
EMIT_PAD( 1 );
#else
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG ))
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, R128_CCE_VC_FRMT_SPEC_FRGB,
1 );
else
EMIT_PAD( 1 );
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
rmesa->specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
R128_CCE_VC_FRMT_SPEC_FRGB, 3 );
} else
EMIT_PAD( 3 );
#endif
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(rmesa->tmu_source[0]) )) {
if ( VB->AttribPtr[_TNL_ATTRIB_TEX0 + rmesa->tmu_source[0]]->size > 2 )
fallback_projtex = GL_TRUE;
EMIT_ATTR( _TNL_ATTRIB_TEX0, EMIT_2F, R128_CCE_VC_FRMT_S_T, 8 );
}
if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(rmesa->tmu_source[1]) )) {
if ( VB->AttribPtr[_TNL_ATTRIB_TEX0 + rmesa->tmu_source[1]]->size > 2 )
fallback_projtex = GL_TRUE;
EMIT_ATTR( _TNL_ATTRIB_TEX1, EMIT_2F, R128_CCE_VC_FRMT_S2_T2, 8 );
}
/* projective textures are not supported by the hardware */
FALLBACK( rmesa, R128_FALLBACK_PROJTEX, fallback_projtex );
/* Only need to change the vertex emit code if there has been a
* statechange to a TNL index.
*/
if (!RENDERINPUTS_EQUAL( index_bitset, rmesa->tnl_state_bitset )) {
FLUSH_BATCH( rmesa );
rmesa->dirty |= R128_UPLOAD_CONTEXT;
rmesa->vertex_size =
_tnl_install_attrs( ctx,
rmesa->vertex_attrs,
rmesa->vertex_attr_count,
rmesa->hw_viewport, 0 );
rmesa->vertex_size >>= 2;
rmesa->vertex_format = vc_frmt;
}
