INLINE u32 RegSRead(RegisterStruct* reg,u32 offset)
{
#ifdef TRACE
if (offset & 3/*(size-1)*/) //4 is min allign size
{
EMUERROR("unallinged register read");
}
#endif
offset>>=2;
#ifdef TRACE
if (reg[offset].flags& size)
{
#endif
if (reg[offset].flags & REG_READ_DATA )
{
if (size==4)
return *reg[offset].data32;
else if (size==2)
return *reg[offset].data16;
else
return *reg[offset].data8;
}
else
{
if (reg[offset].readFunction)
return reg[offset].readFunction();
else
{
if (!(reg[offset].flags& REG_NOT_IMPL))
EMUERROR("ERROR [readed write olny register]");
}
}
#ifdef TRACE
}
else
{
if (!(reg[offset].flags& REG_NOT_IMPL))
EMUERROR("ERROR [wrong size read on register]");
}
#endif
if (reg[offset].flags& REG_NOT_IMPL)
EMUERROR2("Read from internal Regs , not implemented , offset=%x",offset);
return 0;
}
T __fastcall ReadMem_P4(u32 addr)
{
/*if (((addr>>26)&0x7)==7)
{
return ReadMem_area7(addr,sz);
}*/
switch((addr>>24)&0xFF)
{
case 0xE0:
case 0xE1:
case 0xE2:
case 0xE3:
log("Unhandled p4 read [Store queue] 0x%x\n",addr);
return (T)0;
case 0xF0:
//log("Unhandled p4 read [Instruction cache address array] 0x%x\n",addr);
return (T)0;
case 0xF1:
//log("Unhandled p4 read [Instruction cache data array] 0x%x\n",addr);
return (T)0;
case 0xF2:
//log("Unhandled p4 read [Instruction TLB address array] 0x%x\n",addr);
{
u32 entry=(addr>>8)&3;
return (T)(ITLB[entry].Address.reg_data | (ITLB[entry].Data.V<<8));
}
case 0xF3:
//log("Unhandled p4 read [Instruction TLB data arrays 1 and 2] 0x%x\n",addr);
{
u32 entry=(addr>>8)&3;
return (T)ITLB[entry].Data.reg_data;
}
case 0xF4:
{
//int W,Set,A;
//W=(addr>>14)&1;
//A=(addr>>3)&1;
//Set=(addr>>5)&0xFF;
//log("Unhandled p4 read [Operand cache address array] %d:%d,%d 0x%x\n",Set,W,A,addr);
return (T)0;
}
case 0xF5:
//log("Unhandled p4 read [Operand cache data array] 0x%x",addr);
return (T)0;
case 0xF6:
//log("Unhandled p4 read [Unified TLB address array] 0x%x\n",addr);
{
u32 entry=(addr>>8)&63;
u32 rv=UTLB[entry].Address.reg_data;
rv|=UTLB[entry].Data.D<<9;
rv|=UTLB[entry].Data.V<<8;
return (T)rv;
}
case 0xF7:
//log("Unhandled p4 read [Unified TLB data arrays 1 and 2] 0x%x\n",addr);
{
u32 entry=(addr>>8)&63;
return (T)UTLB[entry].Data.reg_data;
}
case 0xFF:
log("Unhandled p4 read [area7] 0x%x\n",addr);
break;
default:
log("Unhandled p4 read [Reserved] 0x%x\n",addr);
break;
}
EMUERROR2("Read from P4 not implemented , addr=%x",addr);
return (T)0;
}
T DYNACALL ReadMem_area0(u32 addr)
{
addr &= 0x01FFFFFF;//to get rid of non needed bits
const u32 base=(addr>>16);
//map 0x0000 to 0x01FF to Default handler
//mirror 0x0200 to 0x03FF , from 0x0000 to 0x03FFF
//map 0x0000 to 0x001F
if (base<=0x001F)// :MPX System/Boot ROM
{
return ReadBios(addr,sz);
}
//map 0x0020 to 0x0021
else if ((base>= 0x0020) && (base<= 0x0021)) // :Flash Memory
{
return ReadFlash(addr&0x1FFFF,sz);
}
//map 0x005F to 0x005F
else if (likely(base==0x005F))
{
if ( /*&& (addr>= 0x00400000)*/ (addr<= 0x005F67FF)) // :Unassigned
{
EMUERROR2("Read from area0_32 not implemented [Unassigned], addr=%x",addr);
}
else if ((addr>= 0x005F7000) && (addr<= 0x005F70FF)) // GD-ROM
{
//EMUERROR3("Read from area0_32 not implemented [GD-ROM], addr=%x,size=%d",addr,sz);
#if DC_PLATFORM == DC_PLATFORM_NAOMI
return (T)ReadMem_naomi(addr,sz);
#else
return (T)ReadMem_gdrom(addr,sz);
#endif
}
else if (likely((addr>= 0x005F6800) && (addr<=0x005F7CFF))) // /*:PVR i/f Control Reg.*/ -> ALL SB registers now
{
//EMUERROR2("Read from area0_32 not implemented [PVR i/f Control Reg], addr=%x",addr);
return (T)sb_ReadMem(addr,sz);
}
else if (likely((addr>= 0x005F8000) && (addr<=0x005F9FFF))) // :TA / PVR Core Reg.
{
//EMUERROR2("Read from area0_32 not implemented [TA / PVR Core Reg], addr=%x",addr);
if (sz != 4)
// House of the Dead 2
return 0;
return (T)pvr_ReadReg(addr);
}
}
//map 0x0060 to 0x0060
else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // :MODEM
{
return (T)libExtDevice_ReadMem_A0_006(addr,sz);
//EMUERROR2("Read from area0_32 not implemented [MODEM], addr=%x",addr);
}
//map 0x0060 to 0x006F
else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // :G2 (Reserved)
{
EMUERROR2("Read from area0_32 not implemented [G2 (Reserved)], addr=%x",addr);
}
//map 0x0070 to 0x0070
else if ((base ==0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // :AICA- Sound Cntr. Reg.
{
//EMUERROR2("Read from area0_32 not implemented [AICA- Sound Cntr. Reg], addr=%x",addr);
return (T) ReadMem_aica_reg(addr,sz);//libAICA_ReadReg(addr,sz);
}
//map 0x0071 to 0x0071
else if ((base ==0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // :AICA- RTC Cntr. Reg.
{
//EMUERROR2("Read from area0_32 not implemented [AICA- RTC Cntr. Reg], addr=%x",addr);
return (T)ReadMem_aica_rtc(addr,sz);
}
//map 0x0080 to 0x00FF
else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // :AICA- Wave Memory
{
//EMUERROR2("Read from area0_32 not implemented [AICA- Wave Memory], addr=%x",addr);
//return (T)libAICA_ReadMem_aica_ram(addr,sz);
ReadMemArrRet(aica_ram.data,addr&ARAM_MASK,sz);
}
//map 0x0100 to 0x01FF
else if ((base >=0x0100) && (base <=0x01FF) /*&& (addr>= 0x01000000) && (addr<= 0x01FFFFFF)*/) // :Ext. Device
{
// EMUERROR2("Read from area0_32 not implemented [Ext. Device], addr=%x",addr);
return (T)libExtDevice_ReadMem_A0_010(addr,sz);
}
return 0;
}
