void EEPROMWriteByte(WORD addr, BYTE value)
{
BYTE i = 0;
BYTE xdata ee_str[3];
if(DB_Addr)
ee_str[i++] = MSB(addr); // if 16 bit, we need 2-byte address and 1 byte data
ee_str[i++] = LSB(addr);
ee_str[i++] = value;
LED=1;
EZUSB_WriteI2C(I2C_Addr, i, ee_str);
LED=0;
EZUSB_WaitForEEPROMWrite(I2C_Addr);
}
void EEPROMRead(WORD addr, BYTE length, BYTE xdata *buf)
{
BYTE i = 0;
BYTE j = 0;
BYTE xdata ee_str[2];
if(DB_Addr)
ee_str[i++] = MSB(addr);
ee_str[i++] = LSB(addr);
EZUSB_WriteI2C(I2C_Addr, i, ee_str);
for(j=0; j < length; j++)
*(buf+j) = 0xcd;
EZUSB_ReadI2C(I2C_Addr, length, buf);
}
void EEPROMWriteByte(WORD addr, BYTE value)
{
BYTE i = 0;
BYTE xdata ee_str[3];
if(DB_Addr)
ee_str[i++] = MSB(addr); // if 16 bit, we need 2-byte address and 1 byte data
ee_str[i++] = LSB(addr);
ee_str[i++] = value;
//EZUSB_WriteI2C(I2C_Addr, i, ee_str);
// http://www.keil.com/forum/docs/thread11160.asp
while( I2CPckt.status != I2C_IDLE ); // wait for write session
while(EZUSB_WriteI2C( I2C_Addr, i, ee_str )!=I2C_OK);
EZUSB_WaitForEEPROMWrite( I2C_Addr ); // wait for Write Cycle Time
// LED=1;
}
void DSLogic_Poll(void)
{
if (cfg_init && EP0BCL == sizeof(struct cmd_cfg_count))
{
cfg_init = FALSE;
init_config_intf();
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
GPIFIDLECTL &= 0xFB; //PROG_B signal low
EZUSB_Delay1ms(); //PROG_B signal kept asserted for 1 ms
GPIFIDLECTL |= 0x04; //PROG_B signal high
SYNCDELAY;
// setup transaction count
GPIFTCB0 = ((const struct cmd_cfg_count *)EP0BUF)->byte0;
SYNCDELAY;
GPIFTCB1 = ((const struct cmd_cfg_count *)EP0BUF)->byte1;
SYNCDELAY;
GPIFTCB2 = ((const struct cmd_cfg_count *)EP0BUF)->byte2;
SYNCDELAY;
cfg_enable = TRUE;
}
if (cfg_enable && (GPIFTRIG & 0x80)) // if GPIF interface IDLE
{
if ( (EP24FIFOFLGS & 0x01) && (GPIFREADYSTAT & 0x01)) {
// if there's a packet in the peripheral domain for EP2
// and FPGA is ready to receive the configuration bitstream
IFCONFIG = 0xA6;
// 7 IFCLKSRC=1 , FIFOs executes on internal clk source
// 6 xMHz=0 , 30MHz internal clk rate
// 5 IFCLKOE=1 , Drive IFCLK pin signal at 30MHz
// 4 IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// 3 ASYNC=0 , master samples asynchronous
// 2 GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// 1:0 IFCFG=10, FX2 in GPIF master mode
SYNCDELAY;
//delay(1); //avoid CSI_B deasserted during sync words
GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ); // poll GPIFTRIG.7 GPIF Done bit
SYNCDELAY;
cfg_enable= FALSE; //end of configuration
/* Put the FX2 into GPIF master mode and setup the GPIF. */
//init_capture_intf();
if (GPIFREADYSTAT & 0x02) { // FPGA Configure Done
IOA |= 0x01;
IOA &= 0xf5;
EZUSB_Delay1ms();
IOA |= 0x08;
} else {
IOA &= 0xfc;
}
}
}
switch(command)
{
case CMD_START:
{
if ((EP0CS & bmEPBUSY) != 0)
break;
if (EP0BCL == sizeof(struct cmd_start))
{
if ((*(BYTE *)EP0BUF) & CMD_START_FLAGS_STOP)
stop_capture();
else
start_capture();
}
command = 0;
break;
}
case CMD_SETTING:
{
if ((EP0CS & bmEPBUSY) != 0)
break;
if (EP0BCL == sizeof(struct cmd_setting_count))
{
GPIFABORT = 0xff;
SYNCDELAY;
EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word operation
SYNCDELAY;
setting_count_b0 = ((const struct cmd_setting_count *)EP0BUF)->byte0;
setting_count_b1 = ((const struct cmd_setting_count *)EP0BUF)->byte1;
setting_count_b2 = ((const struct cmd_setting_count *)EP0BUF)->byte2;
set_enable = TRUE;
}
command = 0;
break;
}
case CMD_CONTROL:
{
if ((EP0CS & bmEPBUSY) != 0)
break;
if (EP0BCL == sizeof(struct cmd_control))
{
dsoConfig[0] = ((const struct cmd_control *)EP0BUF)->byte0;
dsoConfig[1] = ((const struct cmd_control *)EP0BUF)->byte1;
dsoConfig[2] = ((const struct cmd_control *)EP0BUF)->byte2;
dsoConfig[3] = ((const struct cmd_control *)EP0BUF)->byte3;
set_dso_ctrl = TRUE;
}
command = 0;
break;
}
default:
command = 0;
break;
}
if (set_enable && (GPIFTRIG & 0x80)) { // if GPIF interface IDLE
if (!(EP24FIFOFLGS & 0x02)) {
SYNCDELAY;
GPIFTCB2 = setting_count_b2;
SYNCDELAY;
GPIFTCB1 = setting_count_b1; // fpga setting count
SYNCDELAY;
GPIFTCB0 = setting_count_b0;
SYNCDELAY;
GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ); // poll GPIFTRIG.7 GPIF Done bit
SYNCDELAY;
set_enable= FALSE; //end of configuration
/* Put the FX2 into GPIF master mode and setup the GPIF. */
init_capture_intf();
}
}
if (set_dso_ctrl) {
EZUSB_WriteI2C(0x51, 4, dsoConfig);
set_dso_ctrl = FALSE;
}
poll_intf();
}
