/**
Allocates and fills in the Page Directory and Page Table Entries to
establish a 1:1 Virtual to Physical mapping.
@param[in] StackBase Stack base address.
@param[in] StackSize Stack size.
@return The address of 4 level page map.
**/
UINTN
CreateIdentityMappingPageTables (
IN EFI_PHYSICAL_ADDRESS StackBase,
IN UINTN StackSize
)
{
UINT32 RegEax;
UINT32 RegEdx;
UINT8 PhysicalAddressBits;
EFI_PHYSICAL_ADDRESS PageAddress;
UINTN IndexOfPml4Entries;
UINTN IndexOfPdpEntries;
UINTN IndexOfPageDirectoryEntries;
UINT32 NumberOfPml4EntriesNeeded;
UINT32 NumberOfPdpEntriesNeeded;
PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
PAGE_TABLE_ENTRY *PageDirectoryEntry;
UINTN TotalPagesNum;
UINTN BigPageAddress;
VOID *Hob;
BOOLEAN Page1GSupport;
PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
Page1GSupport = FALSE;
if (PcdGetBool(PcdUse1GPageTable)) {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000001) {
AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & BIT26) != 0) {
Page1GSupport = TRUE;
}
}
}
//
// Get physical address bits supported.
//
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
} else {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax;
} else {
PhysicalAddressBits = 36;
}
}
//
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
//
ASSERT (PhysicalAddressBits <= 52);
if (PhysicalAddressBits > 48) {
PhysicalAddressBits = 48;
}
//
// Calculate the table entries needed.
//
if (PhysicalAddressBits <= 39 ) {
NumberOfPml4EntriesNeeded = 1;
NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
} else {
NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
NumberOfPdpEntriesNeeded = 512;
}
//
// Pre-allocate big pages to avoid later allocations.
//
if (!Page1GSupport) {
TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
} else {
TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
}
BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);
ASSERT (BigPageAddress != 0);
//
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
//
PageMap = (VOID *) BigPageAddress;
BigPageAddress += SIZE_4KB;
PageMapLevel4Entry = PageMap;
PageAddress = 0;
for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {
//
// Each PML4 entry points to a page of Page Directory Pointer entires.
// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
//
PageDirectoryPointerEntry = (VOID *) BigPageAddress;
BigPageAddress += SIZE_4KB;
//
// Make a PML4 Entry
//
PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;
PageMapLevel4Entry->Bits.ReadWrite = 1;
PageMapLevel4Entry->Bits.Present = 1;
if (Page1GSupport) {
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
if (PcdGetBool (PcdSetNxForStack) && (PageAddress < StackBase + StackSize) && ((PageAddress + SIZE_1GB) > StackBase)) {
Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize);
} else {
//
// Fill in the Page Directory entries
//
PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;
PageDirectory1GEntry->Bits.ReadWrite = 1;
PageDirectory1GEntry->Bits.Present = 1;
PageDirectory1GEntry->Bits.MustBe1 = 1;
}
}
} else {
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
//
// Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
//
PageDirectoryEntry = (VOID *) BigPageAddress;
BigPageAddress += SIZE_4KB;
//
// Fill in a Page Directory Pointer Entries
//
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
PageDirectoryPointerEntry->Bits.ReadWrite = 1;
PageDirectoryPointerEntry->Bits.Present = 1;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
if (PcdGetBool (PcdSetNxForStack) && (PageAddress < StackBase + StackSize) && ((PageAddress + SIZE_2MB) > StackBase)) {
//
// Need to split this 2M page that covers stack range.
//
Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
} else {
//
// Fill in the Page Directory entries
//
PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
PageDirectoryEntry->Bits.ReadWrite = 1;
PageDirectoryEntry->Bits.Present = 1;
PageDirectoryEntry->Bits.MustBe1 = 1;
}
}
}
for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
ZeroMem (
PageDirectoryPointerEntry,
sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)
);
}
}
}
//
// For the PML4 entries we are not using fill in a null entry.
//
for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
ZeroMem (
PageMapLevel4Entry,
sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
);
}
if (PcdGetBool (PcdSetNxForStack)) {
EnableExecuteDisableBit ();
}
return (UINTN)PageMap;
}
/**
Transfers control to DxeCore.
This function performs a CPU architecture specific operations to execute
the entry point of DxeCore with the parameters of HobList.
It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
@param DxeCoreEntryPoint The entry point of DxeCore.
@param HobList The start of HobList passed to DxeCore.
**/
VOID
HandOffToDxeCore (
IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
IN EFI_PEI_HOB_POINTERS HobList
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS BaseOfStack;
EFI_PHYSICAL_ADDRESS TopOfStack;
UINTN PageTables;
X64_IDT_GATE_DESCRIPTOR *IdtTable;
UINTN SizeOfTemplate;
VOID *TemplateBase;
EFI_PHYSICAL_ADDRESS VectorAddress;
UINT32 Index;
X64_IDT_TABLE *IdtTableForX64;
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
BOOLEAN BuildPageTablesIa32Pae;
if (IsNullDetectionEnabled ()) {
ClearFirst4KPage (HobList.Raw);
}
Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);
ASSERT_EFI_ERROR (Status);
if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {
//
// Compute the top of the stack we were allocated, which is used to load X64 dxe core.
// Pre-allocate a 32 bytes which confroms to x64 calling convention.
//
// The first four parameters to a function are passed in rcx, rdx, r8 and r9.
// Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the
// register parameters is reserved on the stack, in case the called function
// wants to spill them; this is important if the function is variadic.
//
TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;
//
// x64 Calling Conventions requires that the stack must be aligned to 16 bytes
//
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);
//
// Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA
// memory, it may be corrupted when copying FV to high-end memory
//
AsmWriteGdtr (&gGdt);
//
// Create page table and save PageMapLevel4 to CR3
//
PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE);
//
// End of PEI phase signal
//
PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
ASSERT_EFI_ERROR (Status);
//
// Paging might be already enabled. To avoid conflict configuration,
// disable paging first anyway.
//
AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
AsmWriteCr3 (PageTables);
//
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
//
UpdateStackHob (BaseOfStack, STACK_SIZE);
SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);
Status = PeiServicesAllocatePages (
EfiBootServicesData,
EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE) + SizeOfTemplate * IDT_ENTRY_COUNT),
&VectorAddress
);
ASSERT_EFI_ERROR (Status);
//
// Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that
// it may not be gotten correctly after IDT register is re-written.
//
IdtTableForX64 = (X64_IDT_TABLE *) (UINTN) VectorAddress;
IdtTableForX64->PeiService = GetPeiServicesTablePointer ();
VectorAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (IdtTableForX64 + 1);
IdtTable = IdtTableForX64->IdtTable;
for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {
IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;
IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;
IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;
IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;
IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));
IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));
IdtTable[Index].Reserved = 0;
CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);
AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);
VectorAddress += SizeOfTemplate;
}
gLidtDescriptor.Base = (UINTN) IdtTable;
//
// Disable interrupt of Debug timer, since new IDT table cannot handle it.
//
SaveAndSetDebugTimerInterrupt (FALSE);
AsmWriteIdtr (&gLidtDescriptor);
DEBUG ((
DEBUG_INFO,
"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
__FUNCTION__,
BaseOfStack,
STACK_SIZE
));
//
// Go to Long Mode and transfer control to DxeCore.
// Interrupts will not get turned on until the CPU AP is loaded.
// Call x64 drivers passing in single argument, a pointer to the HOBs.
//
AsmEnablePaging64 (
SYS_CODE64_SEL,
DxeCoreEntryPoint,
(EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),
0,
TopOfStack
);
} else {
//
// Get Vector Hand-off Info PPI and build Guided HOB
//
Status = PeiServicesLocatePpi (
&gEfiVectorHandoffInfoPpiGuid,
0,
NULL,
(VOID **)&VectorHandoffInfoPpi
);
if (Status == EFI_SUCCESS) {
DEBUG ((EFI_D_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));
VectorInfo = VectorHandoffInfoPpi->Info;
Index = 1;
while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
VectorInfo ++;
Index ++;
}
BuildGuidDataHob (
&gEfiVectorHandoffInfoPpiGuid,
VectorHandoffInfoPpi->Info,
sizeof (EFI_VECTOR_HANDOFF_INFO) * Index
);
}
//
// Compute the top of the stack we were allocated. Pre-allocate a UINTN
// for safety.
//
TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
PageTables = 0;
BuildPageTablesIa32Pae = ToBuildPageTable ();
if (BuildPageTablesIa32Pae) {
PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);
if (IsEnableNonExecNeeded ()) {
EnableExecuteDisableBit();
}
}
//
// End of PEI phase signal
//
PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
ASSERT_EFI_ERROR (Status);
if (BuildPageTablesIa32Pae) {
//
// Paging might be already enabled. To avoid conflict configuration,
// disable paging first anyway.
//
AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
AsmWriteCr3 (PageTables);
//
// Set Physical Address Extension (bit 5 of CR4).
//
AsmWriteCr4 (AsmReadCr4 () | BIT5);
}
//
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
//
UpdateStackHob (BaseOfStack, STACK_SIZE);
DEBUG ((
DEBUG_INFO,
"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
__FUNCTION__,
BaseOfStack,
STACK_SIZE
));
//
// Transfer the control to the entry point of DxeCore.
//
if (BuildPageTablesIa32Pae) {
AsmEnablePaging32 (
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
HobList.Raw,
NULL,
(VOID *) (UINTN) TopOfStack
);
} else {
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
HobList.Raw,
NULL,
(VOID *) (UINTN) TopOfStack
);
}
}
}
