/**
* @brief Returns a chip's name and EC level
*
* @param[in] i_attr Attribute ID (just used for tracing)
* @param[in] i_chip Reference to Chip fapi target
* @param[out] o_name Filled in with the chip name
* @param[out] o_ec Filled in with the chip EC level
*
* @return fapi::ReturnCode Indicating success or error
*/
fapi::ReturnCode pllInfoGetChipNameEc(
const fapi::getPllRingInfo::Attr i_attr,
const fapi::Target & i_chip,
fapi::ATTR_NAME_Type & o_name,
fapi::ATTR_EC_Type & o_ec)
{
fapi::ReturnCode l_rc;
// As an Attribute Accessor HWP that needs the chip's name/EC to figure out
// the data to return, it is valid to access these privileged attributes
l_rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_chip, o_name);
if (l_rc)
{
FAPI_ERR("getPllRingInfoAttr: error getting ATTR_NAME for attr %d",
i_attr);
}
else
{
l_rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_chip, o_ec);
if (l_rc)
{
FAPI_ERR("getPllRingInfoAttr: error getting ATTR_EC for attr %d",
i_attr);
}
}
return l_rc;
}
// HWP entry point, comments in header
fapi::ReturnCode proc_tp_collect_dbg_data(const fapi::Target & i_target,
fapi::ReturnCode & o_rc)
{
fapi::ReturnCode rc;
uint32_t rc_ecmd = 0;
uint8_t chip_type;
uint8_t dd_level;
ecmdDataBufferBase ring_data;
ecmdDataBufferBase spy_data;
std::vector<std::pair<uint32_t, uint32_t> > spy_offsets;
ecmdDataBufferBase fsi_data(32);
ecmdDataBufferBase scom_data(64);
// mark HWP entry
FAPI_INF("proc_tp_collect_dbg_data: Start");
do
{
// Setting Prevent AutoStart Bit to avoid scan chain corruption
rc = fapiGetCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_SBE_VITAL_0x0000281c)");
break;
}
rc_ecmd |= fsi_data.setBit(1);
rc_ecmd |= fsi_data.setBit(3);
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI SBE Vital Register",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_SBE_VITAL_0x0000281C)");
break;
}
// Setting FSI Shift Speed
rc = fapiGetCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_SHIFT_CTRL_0x00000C10)");
break;
}
rc_ecmd |= fsi_data.setWord(0,PROC_TP_COLLECT_DBG_DATA_FSI_SHIFT_CTRL);
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI SHIFT CTRL register data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_SHIFT_CTRL_0x00000C10)");
break;
}
// Changing Fences for Vital scan
rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_0x00002812, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_GP3_0x00002812)");
break;
}
rc_ecmd |= fsi_data.clearBit(23);
rc_ecmd |= fsi_data.setBit(24);
rc_ecmd |= fsi_data.setBit(25);
rc_ecmd |= fsi_data.setBit(26);
rc_ecmd |= fsi_data.clearBit(27);
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI GP3 data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_0x00002812, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_GP3_0x00002812)");
break;
}
rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
break;
}
rc_ecmd |= fsi_data.setBit(16);
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI GP3 MIRROR data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
break;
}
rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
break;
}
rc_ecmd |= fsi_data.setBit(26);
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI GP3 MIRROR data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
break;
}
// obtain chip type/EC
rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_target, chip_type);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error from FAPI_ATTR_GET_PRIVILEGED (ATTR_NAME)");
break;
}
rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, dd_level);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error from FAPI_ATTR_GET_PRIVILEGED (ATTR_EC)");
break;
}
// configure ring/spy data buffers & spy extraction offsets based on CT/EC
if ((chip_type == fapi::ENUM_ATTR_NAME_MURANO) && (dd_level < 0x20))
{
rc_ecmd |= ring_data.setBitLength(PERV_VITL_CHAIN_LENGTH_MDD1);
rc_ecmd |= spy_data.setBitLength(TP_VITL_SPY_LENGTH_MDD1);
spy_offsets.assign(TP_VITL_SPY_OFFSETS_MDD1, TP_VITL_SPY_OFFSETS_MDD1 + (sizeof(TP_VITL_SPY_OFFSETS_MDD1) / sizeof(TP_VITL_SPY_OFFSETS_MDD1[0])));
}
else if ((chip_type == fapi::ENUM_ATTR_NAME_MURANO) && (dd_level >= 0x20))
{
rc_ecmd |= ring_data.setBitLength(PERV_VITL_CHAIN_LENGTH_MDD2);
rc_ecmd |= spy_data.setBitLength(TP_VITL_SPY_LENGTH_MDD2);
spy_offsets.assign(TP_VITL_SPY_OFFSETS_MDD2, TP_VITL_SPY_OFFSETS_MDD2 + (sizeof(TP_VITL_SPY_OFFSETS_MDD2) / sizeof(TP_VITL_SPY_OFFSETS_MDD2[0])));
}
else if ((chip_type == fapi::ENUM_ATTR_NAME_VENICE) ||
(chip_type == fapi::ENUM_ATTR_NAME_NAPLES))
{
rc_ecmd |= ring_data.setBitLength(PERV_VITL_CHAIN_LENGTH_VN);
rc_ecmd |= spy_data.setBitLength(TP_VITL_SPY_LENGTH_VN);
spy_offsets.assign(TP_VITL_SPY_OFFSETS_VN, TP_VITL_SPY_OFFSETS_VN + (sizeof(TP_VITL_SPY_OFFSETS_VN) / sizeof(TP_VITL_SPY_OFFSETS_VN[0])));
}
else
{
FAPI_ERR("proc_tp_collect_dbg_data: Unsupported CT/EC combination!");
const uint8_t CT = chip_type;
const uint8_t EC = dd_level;
FAPI_SET_HWP_ERROR(rc, RC_TP_COLLECT_DBG_DATA_UNSUPPORTED_CHIP);
break;
}
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x sizing FFDC data buffers",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
// collect data from ring
rc = fapiGetRing(i_target, PERV_VITL_CHAIN_RING_ADDRESS, ring_data);
if (rc)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error from fapiGetRing (PERV_VITL_CHAIN)");
break;
}
// extract spy data from ring image
uint32_t spy_offset_curr = 0;
for (std::vector<std::pair<uint32_t, uint32_t> >::const_iterator offset = spy_offsets.begin();
offset != spy_offsets.end();
offset++)
{
uint32_t chunk_size = (offset->second - offset->first + 1);
rc_ecmd |= spy_data.insert(ring_data,
spy_offset_curr,
chunk_size,
offset->first);
spy_offset_curr += chunk_size;
}
if (rc_ecmd)
{
FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x forming FFDC spy data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
ecmdDataBufferBase & VITL_DATA = spy_data;
FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_TP_COLLECT_DBG_DATA);
} while(0);
// mark HWP exit
FAPI_INF("proc_tp_collect_dbg_data: End");
return rc;
}
static fapi2::ReturnCode setup_memory_work_around_attributes(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const fapi2::buffer<uint64_t>& i_ecid_part)
{
uint8_t l_version = 0;
fapi2::ATTR_MINI_EC_Type l_miniEc = 0;
fapi2::ATTR_EC_Type l_chipEc = 0;
FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, i_target, l_chipEc));
if( l_chipEc != 0x10 )
{
// Nothing to do if this isn't DD1.0
return fapi2::FAPI2_RC_SUCCESS;
}
i_ecid_part.extractToRight<DD_LEVEL, DD_LEVEL_LEN>(l_version);
// Workarounds for modules which are before 1.02 (memory part 1)
if (l_version < ddLevelMemoryPart1)
{
FAPI_DBG("seeing version < 1.02 (0x%x) setting attributes", l_version);
// All these attributes have 1 as their 'YES' enum value
uint8_t l_value = 1;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_DO_MSS_WR_VREF, i_target, l_value) );
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_DO_MSS_VREF_DAC, i_target, l_value) );
// The value for this is SKIP - we want to skip in sub DD1.02 HW
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_SKIP_HW_VREF_CAL, i_target, l_value) );
}
// Workarounds for modules which are before 1.03 (memory part 2)
if (l_version < ddLevelMemoryPart2)
{
FAPI_DBG("seeing version < 1.03 (0x%x) setting attributes", l_version);
// All these attributes have 1 as their 'YES' enum value
uint8_t l_value = 1;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_DO_MSS_TRAINING_BAD_BITS, i_target, l_value) );
// The value for this is SKIP - we want to skip in sub DD1.03 HW
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_SKIP_RD_VREF_VREFSENSE_OVERRIDE, i_target, l_value) );
}
// Set the Mini-EC level for firmware to consume
switch( l_version )
{
case(dd_101):
l_miniEc = 1;
break;
case(dd_102):
l_miniEc = 2;
break;
case(dd_103):
l_miniEc = 3;
break;
}
FAPI_INF("MiniEC=%d", l_miniEc);
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MINI_EC, i_target, l_miniEc) );
return fapi2::FAPI2_RC_SUCCESS;
fapi_try_exit:
return fapi2::current_err;
}
