void rf_security_set_key(uint8_t *key)
{
uint8_t n,i;
uint16_t key_buf;
// Set AES key
nrk_spin_wait_us(100);
for(i=0; i<8; i++ )
{
key_buf=(key[i]<<8)|key[i+1];
nrk_spin_wait_us(100);
FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_KEY0+(i*2)),2,n);
}
// Set AES nonce to all zeros
nrk_spin_wait_us(100);
for(i=0; i<7; i++ )
{
key_buf=0;
FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_TXNONCE+(i*2)),2,n);
FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_RXNONCE+(i*2)),2,n);
}
// block counter set 1
key_buf=1;
FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_TXNONCE+14),2,n);
FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_RXNONCE+14),2,n);
}
void
cc2420_set_chan_pan_addr(unsigned channel, /* 11 - 26 */
unsigned pan,
unsigned addr,
const u8_t *ieee_addr)
{
/*
* Subtract the base channel (11), multiply by 5, which is the
* channel spacing. 357 is 2405-2048 and 0x4000 is LOCK_THR = 1.
*/
u8_t spiStatusByte;
u16_t f = channel;
int s;
f = 5*(f - 11) + 357 + 0x4000;
/*
* Writing RAM requires crystal oscillator to be stable.
*/
do {
spiStatusByte = cc2420_status();
} while (!(spiStatusByte & (BV(CC2420_XOSC16M_STABLE))));
pan_id = pan;
cc2420_setreg(CC2420_FSCTRL, f);
s = splhigh();
FASTSPI_WRITE_RAM_LE(&pan, CC2420RAM_PANID, 2, f);
FASTSPI_WRITE_RAM_LE(&addr, CC2420RAM_SHORTADDR, 2, f);
if (ieee_addr != NULL)
FASTSPI_WRITE_RAM_LE(ieee_addr, CC2420RAM_IEEEADDR, 8, f);
splx(s);
}
/*---------------------------------------------------------------------------*/
void
cc2420_aes_set_key(uint8_t *key, int index)
{
uint16_t f;
switch(index) {
case 0:
FASTSPI_WRITE_RAM_LE(key, CC2420RAM_KEY0, KEYLEN, f);
break;
case 1:
FASTSPI_WRITE_RAM_LE(key, CC2420RAM_KEY1, KEYLEN, f);
break;
}
}
void rf_addr_decode_set_my_mac(uint16_t my_mac)
{
uint8_t n;
rfSettings.myAddr = my_mac;
nrk_spin_wait_us(500);
FASTSPI_WRITE_RAM_LE(&my_mac, CC2420RAM_SHORTADDR, 2, n);
nrk_spin_wait_us(500);
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_pan_addr(unsigned pan,
unsigned addr,
const uint8_t *ieee_addr)
{
uint16_t f = 0;
/*
* Writing RAM requires crystal oscillator to be stable.
*/
while(!(status() & (BV(CC2420_XOSC16M_STABLE))));
pan_id = pan;
FASTSPI_WRITE_RAM_LE(&pan, CC2420RAM_PANID, 2, f);
FASTSPI_WRITE_RAM_LE(&addr, CC2420RAM_SHORTADDR, 2, f);
if(ieee_addr != NULL) {
FASTSPI_WRITE_RAM_LE(ieee_addr, CC2420RAM_IEEEADDR, 8, f);
}
}
/* Encrypt at most 16 bytes of data. */
static void
cipher16(uint8_t *data, int len)
{
uint16_t f;
len = MIN(len, MAX_DATALEN);
FASTSPI_WRITE_RAM_LE(data, CC2420RAM_SABUF, len, f);
FASTSPI_STROBE(CC2420_SAES);
FASTSPI_READ_RAM_LE(data, CC2420RAM_SABUF, len, f);
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_pan_addr(unsigned pan,
unsigned addr,
const uint8_t *ieee_addr)
{
uint16_t f = 0;
/*
* Writing RAM requires crystal oscillator to be stable.
*/
while(!(status() & (BV(CC2420_XOSC16M_STABLE))));
pan_id = pan;
FASTSPI_WRITE_RAM_LE(&pan, CC2420RAM_PANID, 2, f);
FASTSPI_WRITE_RAM_LE(&addr, CC2420RAM_SHORTADDR, 2, f);
if(ieee_addr != NULL) {
uint8_t addr[8];
/* LSB first, MSB last for 802.15.4 addresses in CC2420 */
for (f = 0; f < 8; f++) {
addr[7 - f] = ieee_addr[f];
}
FASTSPI_WRITE_RAM_LE(addr, CC2420RAM_IEEEADDR, 8, f);
}
}
//-------------------------------------------------------------------------------------------------------
// void rf_init(RF_RX_INFO *pRRI, uint8_t channel, WORD panId, WORD myAddr)
//
// DESCRIPTION:
// Initializes CC2420 for radio communication via the basic RF library functions. Turns on the
// voltage regulator, resets the CC2420, turns on the crystal oscillator, writes all necessary
// registers and protocol addresses (for automatic address recognition). Note that the crystal
// oscillator will remain on (forever).
//
// ARGUMENTS:
// RF_RX_INFO *pRRI
// A pointer the RF_RX_INFO data structure to be used during the first packet reception.
// The structure can be switched upon packet reception.
// uint8_t channel
// The RF channel to be used (11 = 2405 MHz to 26 = 2480 MHz)
// WORD panId
// The personal area network identification number
// WORD myAddr
// The 16-bit short address which is used by this node. Must together with the PAN ID form a
// unique 32-bit identifier to avoid addressing conflicts. Normally, in a 802.15.4 network, the
// short address will be given to associated nodes by the PAN coordinator.
//-------------------------------------------------------------------------------------------------------
void rf_init(RF_RX_INFO *pRRI, uint8_t channel, uint16_t panId, uint16_t myAddr)
{
uint8_t n;
#ifdef RADIO_PRIORITY_CEILING
int8_t v;
radio_sem = nrk_sem_create(1,RADIO_PRIORITY_CEILING);
if (radio_sem == NULL)
nrk_kernel_error_add (NRK_SEMAPHORE_CREATE_ERROR, nrk_get_pid ());
v = nrk_sem_pend (radio_sem);
if (v == NRK_ERROR)
{
nrk_kprintf (PSTR ("CC2420 ERROR: Access to semaphore failed\r\n"));
}
#endif
// Make sure that the voltage regulator is on, and that the reset pin is inactive
SET_VREG_ACTIVE();
halWait(1000);
SET_RESET_ACTIVE();
halWait(1);
SET_RESET_INACTIVE();
halWait(100);
// Initialize the FIFOP external interrupt
//FIFOP_INT_INIT();
//ENABLE_FIFOP_INT();
// Turn off all interrupts while we're accessing the CC2420 registers
DISABLE_GLOBAL_INT();
FASTSPI_STROBE(CC2420_SXOSCON);
mdmctrl0=0x02E2;
FASTSPI_SETREG(CC2420_MDMCTRL0, mdmctrl0); // Std Preamble, CRC, no auto ack, no hw addr decoding
//FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AF2); // Turn on automatic packet acknowledgment
// Turn on hw addre decoding
FASTSPI_SETREG(CC2420_MDMCTRL1, 0x0500); // Set the correlation threshold = 20
FASTSPI_SETREG(CC2420_IOCFG0, 0x007F); // Set the FIFOP threshold to maximum
FASTSPI_SETREG(CC2420_SECCTRL0, 0x01C4); // Turn off "Security"
FASTSPI_SETREG(CC2420_RXCTRL1, 0x1A56); // All default except
// reference bias current to RX
// bandpass filter is set to 3uA
/*
// FIXME: remove later for auto ack
myAddr=MY_MAC;
panId=0x02;
FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AF2); // Turn on automatic packet acknowledgment
// FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AE2); // Turn on automatic packet acknowledgment
nrk_spin_wait_us(500);
nrk_spin_wait_us(500);
FASTSPI_WRITE_RAM_LE(&myAddr, CC2420RAM_SHORTADDR, 2, n);
nrk_spin_wait_us(500);
FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n);
nrk_spin_wait_us(500);
printf( "myAddr=%d\r\n",myAddr );
*/
nrk_spin_wait_us(500);
FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n);
nrk_spin_wait_us(500);
ENABLE_GLOBAL_INT();
// Set the RF channel
halRfSetChannel(channel);
// Turn interrupts back on
ENABLE_GLOBAL_INT();
// Set the protocol configuration
rfSettings.pRxInfo = pRRI;
rfSettings.panId = panId;
rfSettings.myAddr = myAddr;
rfSettings.txSeqNumber = 0;
rfSettings.receiveOn = FALSE;
// Wait for the crystal oscillator to become stable
halRfWaitForCrystalOscillator();
// Write the short address and the PAN ID to the CC2420 RAM (requires that the XOSC is on and stable)
// DISABLE_GLOBAL_INT();
// FASTSPI_WRITE_RAM_LE(&myAddr, CC2420RAM_SHORTADDR, 2, n);
// FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n);
// ENABLE_GLOBAL_INT();
#ifdef RADIO_PRIORITY_CEILING
v = nrk_sem_post (radio_sem);
if (v == NRK_ERROR)
{
nrk_kprintf (PSTR ("CC2420 ERROR: Release of semaphore failed\r\n"));
_nrk_errno_set (2);
}
#endif
auto_ack_enable=0;
security_enable=0;
last_pkt_encrypted=0;
} // rf_init()
