//SRAM初始化配置
void SRAM_Init(void)
{
/* set SRAM pinMux */
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
/* flexbus clock output(optional, use for debug) */
PORTC->PCR[3] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_CLKOUT
/*control signals */
PORTB->PCR[19] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_OE
PORTC->PCR[11] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_RW
PORTD->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // CS1
PORTC->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_BE_23_16
PORTC->PCR[17] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_BE_31-24
/* address signal */
PORTD->PCR[10] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // FB_A18
PORTD->PCR[9] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // FB_A17
PORTD->PCR[8] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // FB_A16
PORTB->PCR[18] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A15
PORTC->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A14
PORTC->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A13
PORTC->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A12
PORTC->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A11
PORTC->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A10
PORTC->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A9
PORTC->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A8
PORTC->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A7
PORTC->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A6
PORTC->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A5
PORTD->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A4
PORTD->PCR[3] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A3
PORTD->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A2
PORTD->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_A1
/* data signal */
PORTB->PCR[17] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD16
PORTB->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD17
PORTB->PCR[11] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD18
PORTB->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD19
PORTB->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD20
PORTB->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD21
PORTB->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD22
PORTB->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD23
PORTC->PCR[15] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD24
PORTC->PCR[14] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD25
PORTC->PCR[13] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD26
PORTC->PCR[12] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD27
PORTB->PCR[23] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD28
PORTB->PCR[22] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD29
PORTB->PCR[21] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD30
PORTB->PCR[20] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD31
/* enable flexbus */
FLEXBUS_InitTypeDef FLEXBUS_InitStruct;
FLEXBUS_InitStruct.ADSpaceMask = kFLEXBUS_ADSpace_512KByte; /* 内存地址范围 512K */
FLEXBUS_InitStruct.autoAckMode = kFLEXBUS_AutoAckEnable; /*启动自动应答 */
FLEXBUS_InitStruct.CSn = kFLEXBUS_CS1; /*使用CS1片选信号 */
FLEXBUS_InitStruct.dataAlignMode = kFLEXBUS_DataLeftAligned; /*数据左对齐 */
FLEXBUS_InitStruct.dataWidth = kFLEXBUS_PortSize_16Bit; /*数据位宽 16位 */
FLEXBUS_InitStruct.baseAddress = SRAM_ADDRESS_BASE; /* 基地址 */
FLEXBUS_InitStruct.ByteEnableMode = kFLEXBUS_BE_AssertedReadWrite; /* 在读写操作的时候都插入 位使能信号 */
FLEXBUS_InitStruct.div = 1;
FLEXBUS_Init(&FLEXBUS_InitStruct);
/* advanced config */
FLEXBUS_AdvancedConfigTypeDef config;
config.kFLEXBUS_brustWriteEnable = false;
config.kFLEXBUS_brustReadEnable = false;
config.kFLEXBUS_EXTS = true;
config.kFLEXBUS_ASET = 0;
config.kFLEXBUS_RDAH = 0;
config.kFLEXBUS_WRAH = 0;
config.kFLEXBUS_WS = 1;
FLEXBUS_AdvancedConfig(FLEXBUS_InitStruct.CSn, &config);
/* config Flexbus SRAM pinmux */
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group3, kFLEXBUS_CSPMCR_GROUP3_BE_23_16);
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group2, kFLEXBUS_CSPMCR_GROUP2_BE_31_24);
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group1, kFLEXBUS_CSPMCR_GROUP1_CS1);
}
void ili9320_init(void)
{
uint32_t gpio_instance;
/* ??flexbus???? ?????? ?????????? */
/* Flexbus Init */
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
/*control signals */
PORTB->PCR[19] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_OE
PORTD->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // CS0
PORTA->PCR[26] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // A27
PORTC->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_BE_23_16
/*
PORTB->PCR[18] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD15
PORTC->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD14
PORTC->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD13
PORTC->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD12
PORTC->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD11
PORTC->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD10
PORTC->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD9
PORTC->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD8
PORTC->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD7
PORTC->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD6
PORTC->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD5
PORTD->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD4
PORTD->PCR[3] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD3
PORTD->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD2
PORTD->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD1
PORTD->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD0
*/
PORTB->PCR[17] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD16
PORTB->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD17
PORTB->PCR[11] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD18
PORTB->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD19
PORTB->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD20
PORTB->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD21
PORTB->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD22
PORTB->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD23
PORTC->PCR[15] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD24
PORTC->PCR[14] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD25
PORTC->PCR[13] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD26
PORTC->PCR[12] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD27
PORTB->PCR[23] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD28
PORTB->PCR[22] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD29
PORTB->PCR[21] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD30
PORTB->PCR[20] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD31
FLEXBUS_InitTypeDef FLEXBUS_InitStruct;
FLEXBUS_InitStruct.ADSpaceMask = 0x800;
FLEXBUS_InitStruct.autoAckMode = kFLEXBUS_AutoAckEnable;
FLEXBUS_InitStruct.CSn = kFLEXBUS_CS0;
FLEXBUS_InitStruct.dataAlignMode = kFLEXBUS_DataLeftAligned;
FLEXBUS_InitStruct.dataWidth = kFLEXBUS_PortSize_16Bit;
FLEXBUS_InitStruct.baseAddress = ILI9320_BASE;
FLEXBUS_InitStruct.ByteEnableMode = kFLEXBUS_BE_AssertedWrite;
FLEXBUS_InitStruct.div = 2;
FLEXBUS_Init(&FLEXBUS_InitStruct);
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group3, kFLEXBUS_CSPMCR_GROUP3_BE_23_16);
/* advanced config */
FLEXBUS_AdvancedConfigTypeDef config;
config.kFLEXBUS_brustWriteEnable = false;
config.kFLEXBUS_brustReadEnable = false;
config.kFLEXBUS_EXTS = true;
config.kFLEXBUS_ASET = 1;
config.kFLEXBUS_RDAH = 1;
config.kFLEXBUS_WRAH = 1;
config.kFLEXBUS_WS = 6;
FLEXBUS_AdvancedConfig(FLEXBUS_InitStruct.CSn, &config);
/* Back light */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 3, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 3, 1);
/* reset */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 19, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 19, 0);
DelayMs(5);
GPIO_WriteBit(gpio_instance, 19, 1);
DelayMs(5);
lcd_id = ili9320_get_id();
switch(lcd_id)
{
case 0x9320:
write_reg(0xe5,0x8000); // Set the internal vcore voltage
write_reg(0x00,0x0001); // start OSC
write_reg(0x2b,0x0010); //Set the frame rate as 80 when the internal resistor is used for oscillator circuit
write_reg(0x01,0x0100); //s720 to s1 ; G1 to G320
write_reg(0x02,0x0700); //set the line inversion
//LCD_WR_REG(0x03,0x1018); //65536 colors
write_reg(0x03,0x1030);
//??
#ifdef LCD_USE_HORIZONTAL
write_reg(0x03,(0<<5)|(0<<4)|(1<<3)|(1<<12));
#else
write_reg(0x03,(1<<5)|(1<<4)|(0<<3)|(1<<12));
#endif
write_reg(0x04,0x0000);
write_reg(0x08,0x0202);
write_reg(0x09,0x0000);
write_reg(0x0a,0x0000);
write_reg(0x0c,0x0000);
write_reg(0x0d,0x0000);
write_reg(0x0f,0x0000);
write_reg(0x50,0x0000);
write_reg(0x51,0x00ef);
write_reg(0x52,0x0000);
write_reg(0x53,0x013f);
write_reg(0x60,0x2700);
write_reg(0x61,0x0001);
write_reg(0x6a,0x0000);
write_reg(0x80,0x0000);
write_reg(0x81,0x0000);
write_reg(0x82,0x0000);
write_reg(0x83,0x0000);
write_reg(0x84,0x0000);
write_reg(0x85,0x0000);
write_reg(0x90,0x0010);
write_reg(0x92,0x0000);
write_reg(0x93,0x0003);
write_reg(0x95,0x0110);
write_reg(0x97,0x0000);
write_reg(0x98,0x0000);
write_reg(0x10,0x0000);
write_reg(0x11,0x0000);
write_reg(0x12,0x0000);
write_reg(0x13,0x0000);
DelayMs(20);
write_reg(0x10,0x17b0);
write_reg(0x11,0x0004);
;
write_reg(0x12,0x013e);
;
write_reg(0x13,0x1f00);
write_reg(0x29,0x000f);
;
write_reg(0x20,0x0000);
write_reg(0x21,0x0000);
write_reg(0x30,0x0204);
write_reg(0x31,0x0001);
write_reg(0x32,0x0000);
write_reg(0x35,0x0206);
write_reg(0x36,0x0600);
write_reg(0x37,0x0500);
write_reg(0x38,0x0505);
write_reg(0x39,0x0407);
write_reg(0x3c,0x0500);
write_reg(0x3d,0x0503);
write_reg(0x07,0x0173);
break;
case 0x8989:
write_reg(0x0000,0x0001);
write_reg(0x0003,0xA8A4);
write_reg(0x000C,0x0000);
write_reg(0x000D,0x080C);
write_reg(0x000E,0x2B00);
write_reg(0x001E,0x00B0);
write_reg(0x0001,0x2B3F);
write_reg(0x0002,0x0600);
write_reg(0x0010,0x0000);
write_reg(0x0011,0x6070);
write_reg(0x0005,0x0000);
write_reg(0x0006,0x0000);
write_reg(0x0016,0xEF1C);
write_reg(0x0017,0x0003);
write_reg(0x0007,0x0233);
write_reg(0x000B,0x0000);
write_reg(0x000F,0x0000);
write_reg(0x0041,0x0000);
write_reg(0x0042,0x0000);
write_reg(0x0048,0x0000);
write_reg(0x0049,0x013F);
write_reg(0x004A,0x0000);
write_reg(0x004B,0x0000);
write_reg(0x0044,0xEF00);
write_reg(0x0045,0x0000);
write_reg(0x0046,0x013F);
write_reg(0x0030,0x0707);
write_reg(0x0031,0x0204);
write_reg(0x0032,0x0204);
write_reg(0x0033,0x0502);
write_reg(0x0034,0x0507);
write_reg(0x0035,0x0204);
write_reg(0x0036,0x0204);
write_reg(0x0037,0x0502);
write_reg(0x003A,0x0302);
write_reg(0x003B,0x0302);
write_reg(0x0023,0x0000);
write_reg(0x0024,0x0000);
write_reg(0x0025,0x8000);
write_reg(0x004f,0);
write_reg(0x004e,0);
break;
default:
break;
}
//????
// ILI9320_TRACE("ID:0x%X\r\n", ili9320_get_id());
ili9320_clear(BLACK);
}
void ili9325_init(void)
{
uint16_t id;
uint32_t gpio_instance;
/* 减低flexbus总线速度 总线速度太高 不能正确执行读点操作 */
/* Flexbus Init */
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
/*control signals */
PORTB->PCR[19] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_OE
PORTD->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // CS1
PORTA->PCR[26] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // A27
PORTC->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_BE_23_16
/*
PORTB->PCR[18] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD15
PORTC->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD14
PORTC->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD13
PORTC->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD12
PORTC->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD11
PORTC->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD10
PORTC->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD9
PORTC->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD8
PORTC->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD7
PORTC->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD6
PORTC->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD5
PORTD->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD4
PORTD->PCR[3] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD3
PORTD->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD2
PORTD->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD1
PORTD->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD0
*/
PORTB->PCR[17] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD16
PORTB->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD17
PORTB->PCR[11] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD18
PORTB->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD19
PORTB->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD20
PORTB->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD21
PORTB->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD22
PORTB->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD23
PORTC->PCR[15] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD24
PORTC->PCR[14] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD25
PORTC->PCR[13] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD26
PORTC->PCR[12] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD27
PORTB->PCR[23] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD28
PORTB->PCR[22] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD29
PORTB->PCR[21] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD30
PORTB->PCR[20] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD31
FLEXBUS_InitTypeDef FLEXBUS_InitStruct;
FLEXBUS_InitStruct.ADSpaceMask = 0x800;
FLEXBUS_InitStruct.autoAckMode = kFLEXBUS_AutoAckEnable;
FLEXBUS_InitStruct.CSn = kFLEXBUS_CS1;
FLEXBUS_InitStruct.dataAlignMode = kFLEXBUS_DataLeftAligned;
FLEXBUS_InitStruct.dataWidth = kFLEXBUS_PortSize_16Bit;
FLEXBUS_InitStruct.baseAddress = ILI9325_BASE;
FLEXBUS_InitStruct.ByteEnableMode = kFLEXBUS_BE_AssertedWrite;
FLEXBUS_InitStruct.div = 4;
FLEXBUS_Init(&FLEXBUS_InitStruct);
/* 配置Flexbus 引脚复用 */
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group3, kFLEXBUS_CSPMCR_GROUP3_BE_23_16);
/* Back light */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 1, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 1, 1);
/* reset */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 18, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 18, 0);
DelayMs(5);
GPIO_WriteBit(gpio_instance, 18, 1);
DelayMs(5);
//************* Start Initial Sequence **********//
write_reg(0x0001, 0x0100); // set SS and SM bit
write_reg(0x0002, 0x0700); // set 1 line inversion
write_reg(0x0003, 0x1030); // set GRAM write direction and BGR=1.
write_reg(0x0004, 0x0000); // Resize register
write_reg(0x0008, 0x0202); // set the back porch and front porch
write_reg(0x0009, 0x0000); // set non-display area refresh cycle ISC[3:0]
write_reg(0x000A, 0x0000); // FMARK function
write_reg(0x000C, 0x0000); // RGB interface setting
write_reg(0x000D, 0x0000); // Frame marker Position
write_reg(0x000F, 0x0000); // RGB interface polarity
//*************Power On sequence ****************//
write_reg(0x0010, 0x0000); // SAP, BT[3:0], AP, DSTB, SLP, STB
write_reg(0x0011, 0x0007); // DC1[2:0], DC0[2:0], VC[2:0]
write_reg(0x0012, 0x0000); // VREG1OUT voltage
write_reg(0x0013, 0x0000); // VDV[4:0] for VCOM amplitude
write_reg(0x0007, 0x0001);
DelayMs(20); // Dis-charge capacitor power voltage
write_reg(0x0010, 0x1690); // SAP, BT[3:0], AP, DSTB, SLP, STB
write_reg(0x0011, 0x0227); // DC1[2:0], DC0[2:0], VC[2:0]
DelayMs(5); // Delay 50ms
write_reg(0x0012, 0x009D); // Internal reference voltage= Vci;
DelayMs(5); // Delay 50ms
write_reg(0x0013, 0x1900); // Set VDV[4:0] for VCOM amplitude
write_reg(0x0029, 0x0025); // Set VCM[5:0] for VCOMH
write_reg(0x002B, 0x000D); // Set Frame Rate
DelayMs(5); // Delay 50ms
write_reg(0x0020, 0x0000); // GRAM horizontal Address
write_reg(0x0021, 0x0000); // GRAM Vertical Address
// ----------- Adjust the Gamma Curve ----------//
write_reg(0x0030, 0x0007);
write_reg(0x0031, 0x0303);
write_reg(0x0032, 0x0003);
write_reg(0x0035, 0x0206);
write_reg(0x0036, 0x0008);
write_reg(0x0037, 0x0406);
write_reg(0x0038, 0x0304);
write_reg(0x0039, 0x0007);
write_reg(0x003C, 0x0602);
write_reg(0x003D, 0x0008);
//------------------ Set GRAM area ---------------//
write_reg(0x0050, 0x0000); // Horizontal GRAM Start Address
write_reg(0x0051, 0x00EF); // Horizontal GRAM End Address
write_reg(0x0052, 0x0000); // Vertical GRAM Start Address
write_reg(0x0053, 0x013F); // Vertical GRAM Start Address
write_reg(0x0060, 0xA700); // Gate Scan Line
write_reg(0x0061, 0x0001); // NDL,VLE, REV
write_reg(0x006A, 0x0000); // set scrolling line
//-------------- Partial Display Control ---------//
write_reg(0x0080, 0x0000);
write_reg(0x0081, 0x0000);
write_reg(0x0082, 0x0000);
write_reg(0x0083, 0x0000);
write_reg(0x0084, 0x0000);
write_reg(0x0085, 0x0000);
//-------------- Panel Control -------------------//
write_reg(0x0090, 0x0010);
write_reg(0x0092, 0x0600);
write_reg(0x0007, 0x0133); // 262K color and display ON
//开启显示
ILI9325_TRACE("ID:0x%X\r\n", ili9325_get_id());
ili9325_clear(RED);
}
void ili9320_init(void)
{
uint32_t gpio_instance;
/* 减低flexbus总线速度 总线速度太高 不能正确执行读点操作 */
/* Flexbus Init */
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
/*control signals */
PORTB->PCR[19] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_OE
PORTD->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // CS0
PORTA->PCR[26] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // A27
PORTC->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_BE_23_16
/*
PORTB->PCR[18] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD15
PORTC->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD14
PORTC->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD13
PORTC->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD12
PORTC->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD11
PORTC->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD10
PORTC->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD9
PORTC->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD8
PORTC->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD7
PORTC->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD6
PORTC->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD5
PORTD->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD4
PORTD->PCR[3] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD3
PORTD->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD2
PORTD->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD1
PORTD->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD0
*/
PORTB->PCR[17] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD16
PORTB->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD17
PORTB->PCR[11] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD18
PORTB->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD19
PORTB->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD20
PORTB->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD21
PORTB->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD22
PORTB->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD23
PORTC->PCR[15] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD24
PORTC->PCR[14] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD25
PORTC->PCR[13] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD26
PORTC->PCR[12] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD27
PORTB->PCR[23] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD28
PORTB->PCR[22] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD29
PORTB->PCR[21] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD30
PORTB->PCR[20] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD31
FLEXBUS_InitTypeDef FLEXBUS_InitStruct;
FLEXBUS_InitStruct.ADSpaceMask = 0x800;
FLEXBUS_InitStruct.autoAckMode = kFLEXBUS_AutoAckEnable;
FLEXBUS_InitStruct.CSn = kFLEXBUS_CS0;
FLEXBUS_InitStruct.dataAlignMode = kFLEXBUS_DataLeftAligned;
FLEXBUS_InitStruct.dataWidth = kFLEXBUS_PortSize_16Bit;
FLEXBUS_InitStruct.baseAddress = ILI9320_BASE;
FLEXBUS_InitStruct.ByteEnableMode = kFLEXBUS_BE_AssertedWrite;
FLEXBUS_InitStruct.div = 2;
FLEXBUS_Init(&FLEXBUS_InitStruct);
/* 配置Flexbus 引脚复用 */
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group3, kFLEXBUS_CSPMCR_GROUP3_BE_23_16);
/* Back light */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 3, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 3, 1);
/* reset */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 19, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 19, 0);
DelayMs(5);
GPIO_WriteBit(gpio_instance, 19, 1);
DelayMs(5);
//LCD_WR_REG(0xe5,0x8000); // Set the internal vcore voltage
write_reg(0x00,0x0001); // start OSC
write_reg(0x2b,0x0010); //Set the frame rate as 80 when the internal resistor is used for oscillator circuit
write_reg(0x01,0x0100); //s720 to s1 ; G1 to G320
write_reg(0x02,0x0700); //set the line inversion
//LCD_WR_REG(0x03,0x1018); //65536 colors
write_reg(0x03,0x1030);
//横屏
#ifdef LCD_USE_HORIZONTAL
write_reg(0x03,(0<<5)|(0<<4)|(1<<3)|(1<<12));
#else
write_reg(0x03,(1<<5)|(1<<4)|(0<<3)|(1<<12));
#endif
write_reg(0x04,0x0000);
write_reg(0x08,0x0202); //specify the line number of front and back porch periods respectively
write_reg(0x09,0x0000);
write_reg(0x0a,0x0000);
write_reg(0x0c,0x0000); //select internal system clock
write_reg(0x0d,0x0000);
write_reg(0x0f,0x0000);
write_reg(0x50,0x0000); //0x50 -->0x53 set windows adress
write_reg(0x51,0x00ef);
write_reg(0x52,0x0000);
write_reg(0x53,0x013f);
write_reg(0x60,0x2700);
write_reg(0x61,0x0001);
write_reg(0x6a,0x0000);
write_reg(0x80,0x0000);
write_reg(0x81,0x0000);
write_reg(0x82,0x0000);
write_reg(0x83,0x0000);
write_reg(0x84,0x0000);
write_reg(0x85,0x0000);
write_reg(0x90,0x0010);
write_reg(0x92,0x0000);
write_reg(0x93,0x0003);
write_reg(0x95,0x0110);
write_reg(0x97,0x0000);
write_reg(0x98,0x0000);
//power setting function
write_reg(0x10,0x0000);
write_reg(0x11,0x0000);
write_reg(0x12,0x0000);
write_reg(0x13,0x0000);
DelayMs(20);
write_reg(0x10,0x17b0);
write_reg(0x11,0x0004);
DelayMs(5);
write_reg(0x12,0x013e);
DelayMs(5);
write_reg(0x13,0x1f00);
write_reg(0x29,0x000f);
DelayMs(5);
write_reg(0x20,0x0000);
write_reg(0x21,0x0000);
//initializing function 2
write_reg(0x30,0x0204);
write_reg(0x31,0x0001);
write_reg(0x32,0x0000);
write_reg(0x35,0x0206);
write_reg(0x36,0x0600);
write_reg(0x37,0x0500);
write_reg(0x38,0x0505);
write_reg(0x39,0x0407);
write_reg(0x3c,0x0500);
write_reg(0x3d,0x0503);
//开启显示
ILI9320_TRACE("ID:0x%X\r\n", ili9320_get_id());
write_reg(0x07,0x0173);
ili9320_clear(BLACK);
}
