C++ (Cpp) FNET_MK_PORT_PCR_MUX Examples

Example #1

File: fnet_mk_eth.c Project: ErikZalm/fnet

/************************************************************************
* NAME: fnet_eth_io_init
*
* DESCRIPTION: Ethernet IO initialization.
*************************************************************************/
void fnet_eth_io_init() 
{
#if FNET_CFG_CPU_MK60N512 || FNET_CFG_CPU_MK70FN1 || FNET_CFG_CPU_MK60FN1
  
    FNET_MK_PORT_MemMapPtr pctl;
    FNET_MK_SIM_MemMapPtr  sim  = (FNET_MK_SIM_MemMapPtr)FNET_MK_SIM_BASE_PTR;
    
    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTA_BASE_PTR;    
    pctl->PCR[12] = 0x00000400;     /* PTA12, RMII0_RXD1/MII0_RXD1      */
    pctl->PCR[13] = 0x00000400;     /* PTA13, RMII0_RXD0/MII0_RXD0      */
    pctl->PCR[14] = 0x00000400;     /* PTA14, RMII0_CRS_DV/MII0_RXDV    */
    pctl->PCR[15] = 0x00000400;     /* PTA15, RMII0_TXEN/MII0_TXEN      */
    pctl->PCR[16] = 0x00000400;     /* PTA16, RMII0_TXD0/MII0_TXD0      */
    pctl->PCR[17] = 0x00000400;     /* PTA17, RMII0_TXD1/MII0_TXD1      */
    
    
    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTB_BASE_PTR;
    pctl->PCR[0] = FNET_MK_PORT_PCR_MUX(4) | FNET_MK_PORT_PCR_ODE_MASK; /* PTB0, RMII0_MDIO/MII0_MDIO   */
    pctl->PCR[1] = FNET_MK_PORT_PCR_MUX(4);                     /* PTB1, RMII0_MDC/MII0_MDC     */
    
    /* Enable clock for ENET module */
    sim->SCGC2 |= FNET_MK_SIM_SCGC2_ENET_MASK;
    
    /*FSL: allow concurrent access to MPU controller. Example: ENET uDMA to SRAM, otherwise bus error*/
    FNET_MK_MPU_CESR = 0;  /* MPU is disabled. All accesses from all bus masters are allowed.*/
    
#endif  

}

Example #2

File: fnet_mk_eth.c Project: SoFiHa/twrk60_fnet_test

/************************************************************************
* NAME: fnet_eth_io_init
*
* DESCRIPTION: Ethernet IO initialization.
*************************************************************************/
void fnet_eth_io_init(void)
{
    FNET_MK_PORT_MemMapPtr pctl;
    FNET_MK_SIM_MemMapPtr  sim  = (FNET_MK_SIM_MemMapPtr)FNET_MK_SIM_BASE_PTR;

#if FNET_CFG_CPU_MK64FN1

    /* Enable clock */
    FNET_MK_SIM_SCGC5 |= FNET_MK_SIM_SCGC5_PORTC_MASK | FNET_MK_SIM_SCGC5_PORTA_MASK | FNET_MK_SIM_SCGC5_PORTB_MASK;

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTC_BASE_PTR;
    pctl->PCR[16] = 0x00000400u;
    pctl->PCR[17] = 0x00000400u;
    pctl->PCR[18] = 0x00000400u;
    pctl->PCR[19] = 0x00000400u;


    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTA_BASE_PTR;
    pctl->PCR[12] = 0x00000400u;     /* PTA12, RMII0_RXD1/MII0_RXD1      */
    pctl->PCR[13] = 0x00000400u;     /* PTA13, RMII0_RXD0/MII0_RXD0      */
    pctl->PCR[14] = 0x00000400u;     /* PTA14, RMII0_CRS_DV/MII0_RXDV    */
    pctl->PCR[15] = 0x00000400u;     /* PTA15, RMII0_TXEN/MII0_TXEN      */
    pctl->PCR[16] = 0x00000400u;     /* PTA16, RMII0_TXD0/MII0_TXD0      */
    pctl->PCR[17] = 0x00000400u;     /* PTA17, RMII0_TXD1/MII0_TXD1      */
    pctl->PCR[5] = 0x00000400u;
    pctl->PCR[28] = 0x00000400u;

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTB_BASE_PTR;
    pctl->PCR[0] = FNET_MK_PORT_PCR_MUX(4) | FNET_MK_PORT_PCR_ODE_MASK | FNET_MK_PORT_PCR_PS_MASK | FNET_MK_PORT_PCR_PE_MASK; /* PTB0, RMII0_MDIO/MII0_MDIO   */
    pctl->PCR[1] = FNET_MK_PORT_PCR_MUX(4);                     /* PTB1, RMII0_MDC/MII0_MDC     */

#elif FNET_CFG_CPU_MK66FN2

   /* Enable clock */
    FNET_MK_SIM_SCGC5 |= FNET_MK_SIM_SCGC5_PORTE_MASK | FNET_MK_SIM_SCGC5_PORTA_MASK | FNET_MK_SIM_SCGC5_PORTB_MASK;

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTE_BASE_PTR;
    pctl->PCR[26] = 0x00000200u;

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTA_BASE_PTR;
    pctl->PCR[5] = 0x00000400u;
    pctl->PCR[12] = 0x00000400u;     /* PTA12, RMII0_RXD1/MII0_RXD1      */
    pctl->PCR[13] = 0x00000400u;     /* PTA13, RMII0_RXD0/MII0_RXD0      */
    pctl->PCR[14] = 0x00000400u;     /* PTA14, RMII0_CRS_DV/MII0_RXDV    */
    pctl->PCR[15] = 0x00000400u;     /* PTA15, RMII0_TXEN/MII0_TXEN      */
    pctl->PCR[16] = 0x00000400u;     /* PTA16, RMII0_TXD0/MII0_TXD0      */
    pctl->PCR[17] = 0x00000400u;     /* PTA17, RMII0_TXD1/MII0_TXD1      */
    pctl->PCR[28] = 0x00000400u;

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTB_BASE_PTR;
    pctl->PCR[0] = FNET_MK_PORT_PCR_MUX(4) | FNET_MK_PORT_PCR_ODE_MASK | FNET_MK_PORT_PCR_PS_MASK | FNET_MK_PORT_PCR_PE_MASK; /* PTB0, RMII0_MDIO/MII0_MDIO   */
    pctl->PCR[1] = FNET_MK_PORT_PCR_MUX(4);                     /* PTB1, RMII0_MDC/MII0_MDC     */

    /* Set RMII clock src. */
    sim->SOPT2 |= FNET_MK_SIM_SOPT2_RMIISRC(1);

#else /* TWR */
    /* Enable clock */
    FNET_MK_SIM_SCGC5 |= FNET_MK_SIM_SCGC5_PORTA_MASK | FNET_MK_SIM_SCGC5_PORTB_MASK;

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTA_BASE_PTR;
    pctl->PCR[12] = 0x00000400u;     /* PTA12, RMII0_RXD1/MII0_RXD1      */
    pctl->PCR[13] = 0x00000400u;     /* PTA13, RMII0_RXD0/MII0_RXD0      */
    pctl->PCR[14] = 0x00000400u;     /* PTA14, RMII0_CRS_DV/MII0_RXDV    */
    pctl->PCR[15] = 0x00000400u;     /* PTA15, RMII0_TXEN/MII0_TXEN      */
    pctl->PCR[16] = 0x00000400u;     /* PTA16, RMII0_TXD0/MII0_TXD0      */
    pctl->PCR[17] = 0x00000400u;     /* PTA17, RMII0_TXD1/MII0_TXD1      */

    pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTB_BASE_PTR;
    pctl->PCR[0] = FNET_MK_PORT_PCR_MUX(4) | FNET_MK_PORT_PCR_ODE_MASK; /* PTB0, RMII0_MDIO/MII0_MDIO   */
    pctl->PCR[1] = FNET_MK_PORT_PCR_MUX(4);                     /* PTB1, RMII0_MDC/MII0_MDC     */

#endif

    /* Enable clock for ENET module */
    sim->SCGC2 |= FNET_MK_SIM_SCGC2_ENET_MASK;

    /*Allow concurrent access to MPU controller. Example: ENET uDMA to SRAM, otherwise bus error*/
    FNET_MK_MPU_CESR = 0u;  /* MPU is disabled. All accesses from all bus masters are allowed.*/
}