static int fs_eth_init(SysBusDevice *dev)
{
struct fs_eth *s = FROM_SYSBUS(typeof(*s), dev);
int eth_regs;
if (!s->dma_out || !s->dma_in) {
hw_error("Unconnected ETRAX-FS Ethernet MAC.\n");
}
s->dma_out->client.push = eth_tx_push;
s->dma_out->client.opaque = s;
s->dma_in->client.opaque = s;
s->dma_in->client.pull = NULL;
eth_regs = cpu_register_io_memory(eth_read, eth_write, s,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x5c, eth_regs);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
tdk_init(&s->phy);
mdio_attach(&s->mdio_bus, &s->phy, s->phyaddr);
return 0;
}
static int realview_mpcore_init(SysBusDevice *dev)
{
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
DeviceState *gic;
DeviceState *priv;
int n;
int i;
priv = qdev_create(NULL, "arm11mpcore_priv");
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
qdev_init_nofail(priv);
s->priv = SYS_BUS_DEVICE(priv);
sysbus_pass_irq(dev, s->priv);
for (i = 0; i < 32; i++) {
s->cpuic[i] = qdev_get_gpio_in(priv, i);
}
/* ??? IRQ routing is hardcoded to "normal" mode. */
for (n = 0; n < 4; n++) {
gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
s->cpuic[10 + n]);
for (i = 0; i < 64; i++) {
s->rvic[n][i] = qdev_get_gpio_in(gic, i);
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
return 0;
}
static int q35_host_init(SysBusDevice *dev)
{
PCIBus *b;
PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci,
"pci-conf-idx", 4);
sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci,
"pci-conf-data", 4);
sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
if (pcie_host_init(&s->host) < 0) {
return -1;
}
b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
s->mch.pci_address_space, s->mch.address_space_io,
0, TYPE_PCIE_BUS);
s->host.pci.bus = b;
qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
qdev_init_nofail(DEVICE(&s->mch));
return 0;
}
static int f2xx_flash_init(SysBusDevice *dev)
{
f2xx_flash_t *flash = FROM_SYSBUS(typeof(*flash), dev);
// memory_region_init_rom_device(&flash->mem, &f2xx_flash_ops, flash, "name",
// size);
memory_region_init_ram(&flash->mem, NULL, "f2xx.flash", flash->size);
vmstate_register_ram(&flash->mem, DEVICE(flash));
//vmstate_register_ram_global(&flash->mem);
memory_region_set_readonly(&flash->mem, true);
memory_region_add_subregion(get_system_memory(), flash->base_address, &flash->mem);
// sysbus_init_mmio(dev, &flash->mem);
flash->data = memory_region_get_ram_ptr(&flash->mem);
memset(flash->data, 0xff, flash->size);
if (flash->bdrv) {
int r;
r = bdrv_read(flash->bdrv, 0, flash->data, bdrv_getlength(flash->bdrv)/BDRV_SECTOR_SIZE);
if (r < 0) {
vmstate_unregister_ram(&flash->mem, DEVICE(flash));
memory_region_destroy(&flash->mem);
return 1;
}
}
return 0;
}
static void tusb6010_reset(DeviceState *dev)
{
TUSBState *s = FROM_SYSBUS(TUSBState, SYS_BUS_DEVICE(dev));
int i;
s->test_reset = TUSB_PROD_TEST_RESET_VAL;
s->host_mode = 0;
s->dev_config = 0;
s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
s->power = 0;
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
s->scratch = 0;
s->prcm_config = 0;
s->prcm_mngmt = 0;
s->intr_ok = 0;
s->usbip_intr = 0;
s->usbip_mask = 0;
s->gpio_intr = 0;
s->gpio_mask = 0;
s->gpio_config = 0;
s->dma_intr = 0;
s->dma_mask = 0;
s->dma_map = 0;
s->dma_config = 0;
s->ep0_config = 0;
s->wkup_mask = 0;
s->pullup[0] = s->pullup[1] = 0;
s->control_config = 0;
for (i = 0; i < 15; i++) {
s->rx_config[i] = s->tx_config[i] = 0;
}
musb_reset(s->musb);
}
static int tcx_init1(SysBusDevice *dev)
{
TCXState *s = FROM_SYSBUS(TCXState, dev);
int io_memory, dummy_memory;
ram_addr_t vram_offset;
int size;
uint8_t *vram_base;
vram_offset = qemu_ram_alloc(s->vram_size * (1 + 4 + 4));
vram_base = qemu_get_ram_ptr(vram_offset);
s->vram_offset = vram_offset;
/* 8-bit plane */
s->vram = vram_base;
size = s->vram_size;
sysbus_init_mmio(dev, size, s->vram_offset);
vram_offset += size;
vram_base += size;
/* DAC */
io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s);
sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory);
/* TEC (dummy) */
dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write,
s);
sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory);
/* THC: NetBSD writes here even with 8-bit display: dummy */
sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory);
if (s->depth == 24) {
/* 24-bit plane */
size = s->vram_size * 4;
s->vram24 = (uint32_t *)vram_base;
s->vram24_offset = vram_offset;
sysbus_init_mmio(dev, size, vram_offset);
vram_offset += size;
vram_base += size;
/* Control plane */
size = s->vram_size * 4;
s->cplane = (uint32_t *)vram_base;
s->cplane_offset = vram_offset;
sysbus_init_mmio(dev, size, vram_offset);
s->ds = graphic_console_init(tcx24_update_display,
tcx24_invalidate_display,
tcx24_screen_dump, NULL, s);
} else {
/* THC 8 bit (dummy) */
sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory);
s->ds = graphic_console_init(tcx_update_display,
tcx_invalidate_display,
tcx_screen_dump, NULL, s);
}
qemu_console_resize(s->ds, s->width, s->height);
return 0;
}
static int realview_gic_init(SysBusDevice *dev)
{
RealViewGICState *s = FROM_SYSBUS(RealViewGICState, dev);
SysBusDevice *busdev;
/* The GICs on the RealView boards have a fixed nonconfigurable
* number of interrupt lines, so we don't need to expose this as
* a qdev property.
*/
int numirq = 96;
s->gic = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", 1);
qdev_prop_set_uint32(s->gic, "num-irq", numirq);
qdev_init_nofail(s->gic);
busdev = sysbus_from_qdev(s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, busdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32);
memory_region_init(&s->container, "realview-gic-container", 0x2000);
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(busdev, 1));
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
sysbus_init_mmio(dev, &s->container);
return 0;
}
static int fs_eth_init(SysBusDevice *dev)
{
struct fs_eth *s = FROM_SYSBUS(typeof(*s), dev);
if (!s->dma_out || !s->dma_in) {
hw_error("Unconnected ETRAX-FS Ethernet MAC.\n");
}
s->dma_out->client.push = eth_tx_push;
s->dma_out->client.opaque = s;
s->dma_in->client.opaque = s;
s->dma_in->client.pull = NULL;
memory_region_init_io(&s->mmio, ð_ops, s, "etraxfs-eth", 0x5c);
sysbus_init_mmio(dev, &s->mmio);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,
object_get_typename(OBJECT(s)), dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
tdk_init(&s->phy);
mdio_attach(&s->mdio_bus, &s->phy, s->phyaddr);
return 0;
}
static int arm_mptimer_init(SysBusDevice *dev)
{
ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev);
int i;
if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
}
/* We implement one timer block per CPU, and expose multiple MMIO regions:
* * region 0 is "timer for this core"
* * region 1 is "timer for core 0"
* * region 2 is "timer for core 1"
* and so on.
* The outgoing interrupt lines are
* * timer for core 0
* * timer for core 1
* and so on.
*/
memory_region_init_io(&s->iomem, OBJECT(s), &arm_thistimer_ops, s,
"arm_mptimer_timer", 0x20);
sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < s->num_cpu; i++) {
TimerBlock *tb = &s->timerblock[i];
tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
sysbus_init_irq(dev, &tb->irq);
memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
"arm_mptimer_timerblock", 0x20);
sysbus_init_mmio(dev, &tb->iomem);
}
return 0;
}
static int milkymist_ac97_init(SysBusDevice *dev)
{
MilkymistAC97State *s = FROM_SYSBUS(typeof(*s), dev);
struct audsettings as;
sysbus_init_irq(dev, &s->crrequest_irq);
sysbus_init_irq(dev, &s->crreply_irq);
sysbus_init_irq(dev, &s->dmar_irq);
sysbus_init_irq(dev, &s->dmaw_irq);
AUD_register_card("Milkymist AC'97", &s->card);
as.freq = 48000;
as.nchannels = 2;
as.fmt = AUD_FMT_S16;
as.endianness = 1;
s->voice_in = AUD_open_in(&s->card, s->voice_in,
"mm_ac97.in", s, ac97_in_cb, &as);
s->voice_out = AUD_open_out(&s->card, s->voice_out,
"mm_ac97.out", s, ac97_out_cb, &as);
memory_region_init_io(&s->regs_region, &ac97_mmio_ops, s,
"milkymist-ac97", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}
static int cadence_uart_init(SysBusDevice *dev)
{
UartState *s = FROM_SYSBUS(UartState, dev);
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock,
(QEMUTimerCB *)fifo_trigger_update, s);
s->tx_time_handle = qemu_new_timer_ns(vm_clock,
(QEMUTimerCB *)uart_tx_write, s);
s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
s->chr = qemu_char_get_next_serial();
cadence_uart_reset(s);
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
uart_event, s);
}
return 0;
}
static int pci_vpb_init(SysBusDevice *dev)
{
PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
PCIBus *bus;
int i;
for (i = 0; i < 4; i++) {
sysbus_init_irq(dev, &s->irq[i]);
}
bus = pci_register_bus(&dev->qdev, "pci",
pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
get_system_memory(), get_system_io(),
PCI_DEVFN(11, 0), 4);
/* ??? Register memory space. */
/* Our memory regions are:
* 0 : PCI self config window
* 1 : PCI config window
* 2 : PCI IO window (realview_pci only)
*/
memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
"pci-vpb-selfconfig", 0x1000000);
sysbus_init_mmio(dev, &s->mem_config);
memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
"pci-vpb-config", 0x1000000);
sysbus_init_mmio(dev, &s->mem_config2);
if (s->realview) {
isa_mmio_setup(&s->isa, 0x0100000);
sysbus_init_mmio(dev, &s->isa);
}
pci_create_simple(bus, -1, "versatile_pci_host");
return 0;
}
static int kvmclock_init(SysBusDevice *dev)
{
KVMClockState *s = FROM_SYSBUS(KVMClockState, dev);
qemu_add_vm_change_state_handler(kvmclock_vm_state_change, s);
return 0;
}
static int mpcore_priv_init(SysBusDevice *dev)
{
ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev);
s->gic = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
/* Request the legacy 11MPCore GIC behaviour: */
qdev_prop_set_uint32(s->gic, "revision", 0);
qdev_init_nofail(s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic));
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32);
s->mptimer = qdev_create(NULL, "arm_mptimer");
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
qdev_init_nofail(s->mptimer);
s->wdtimer = qdev_create(NULL, "arm_mptimer");
qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu);
qdev_init_nofail(s->wdtimer);
mpcore_priv_map_setup(s);
sysbus_init_mmio(dev, &s->container);
return 0;
}
static int fw_cfg_init1(SysBusDevice *dev)
{
FWCfgState *s = FROM_SYSBUS(FWCfgState, dev);
memory_region_init_io(&s->ctl_iomem, &fw_cfg_ctl_mem_ops, s,
"fwcfg.ctl", FW_CFG_SIZE);
sysbus_init_mmio(dev, &s->ctl_iomem);
memory_region_init_io(&s->data_iomem, &fw_cfg_data_mem_ops, s,
"fwcfg.data", FW_CFG_DATA_SIZE);
sysbus_init_mmio(dev, &s->data_iomem);
/* In case ctl and data overlap: */
memory_region_init_io(&s->comb_iomem, &fw_cfg_comb_mem_ops, s,
"fwcfg", FW_CFG_SIZE);
if (s->ctl_iobase + 1 == s->data_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->comb_iomem);
} else {
if (s->ctl_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->ctl_iomem);
}
if (s->data_iobase) {
sysbus_add_io(dev, s->data_iobase, &s->data_iomem);
}
}
return 0;
}
static int s5l8930_spi_init1(SysBusDevice *dev)
{
int iomemtype;
DriveInfo *dinfo;
S5L8930SPIState *s = FROM_SYSBUS(S5L8930SPIState, dev);
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(s5l8930_spi_readfn, s5l8930_spi_writefn, s, DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x3c, iomemtype);
if(!intnum) {
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo) {
fprintf(stderr, "A NOR image must be given with the -pflash parameter\n");
exit(1);
}
s->timer = qemu_new_timer_ns(vm_clock, spi_timer, s);
s->pflash = (void *)pflash_spi_register(qemu_ram_alloc(NULL, "ipad1g.xor", 1024*1024),
dinfo->bdrv, 4096,
256, 1, 2,
0x1f, 0x45, 0x02);
intnum++;
}
return 0;
}
static void arm_sysctl_reset(DeviceState *d)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
int i;
s->leds = 0;
s->lockval = 0;
s->cfgdata1 = 0;
s->cfgdata2 = 0;
s->flags = 0;
s->resetlevel = 0;
/* Motherboard oscillators (in Hz) */
s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
/* Daughterboard oscillators: reset from property values */
for (i = 0; i < s->db_num_clocks; i++) {
s->db_clock[i] = s->db_clock_reset[i];
}
if (board_id(s) == BOARD_ID_VEXPRESS) {
/* On VExpress this register will RAZ/WI */
s->sys_clcd = 0;
} else {
/* All others: CLCDID 0x1f, indicating VGA */
s->sys_clcd = 0x1f00;
}
}
static int xilinx_timer_init(SysBusDevice *dev)
{
struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
unsigned int i;
/* All timers share a single irq line. */
sysbus_init_irq(dev, &t->irq);
/* Init all the ptimers. */
t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
for (i = 0; i < num_timers(t); i++) {
struct xlx_timer *xt = &t->timers[i];
xt->parent = t;
xt->nr = i;
xt->bh = qemu_bh_new(timer_hit, xt);
xt->ptimer = ptimer_init(xt->bh);
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx.xps-timer",
R_MAX * 4 * num_timers(t));
sysbus_init_mmio(dev, &t->mmio);
return 0;
}
static int grlib_gptimer_init(SysBusDevice *dev)
{
GPTimerUnit *unit = FROM_SYSBUS(typeof(*unit), dev);
unsigned int i;
assert(unit->nr_timers > 0);
assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
for (i = 0; i < unit->nr_timers; i++) {
GPTimer *timer = &unit->timers[i];
timer->unit = unit;
timer->bh = qemu_bh_new(grlib_gptimer_hit, timer);
timer->ptimer = ptimer_init(timer->bh);
timer->id = i;
/* One IRQ line for each timer */
sysbus_init_irq(dev, &timer->irq);
ptimer_set_freq(timer->ptimer, unit->freq_hz);
}
memory_region_init_io(&unit->iomem, &grlib_gptimer_ops, unit, "gptimer",
UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
sysbus_init_mmio(dev, &unit->iomem);
return 0;
}
static int xilinx_spi_init(SysBusDevice *dev)
{
int i;
XilinxSPI *s = FROM_SYSBUS(typeof(*s), dev);
DB_PRINT("\n");
s->spi = ssi_create_bus(&dev->qdev, "spi");
sysbus_init_irq(dev, &s->irq);
s->cs_lines = g_new(qemu_irq, s->num_cs);
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi);
for (i = 0; i < s->num_cs; ++i) {
sysbus_init_irq(dev, &s->cs_lines[i]);
}
memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
"xilinx-spi", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->irqline = -1;
fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
return 0;
}
static int arm_gic_common_init(SysBusDevice *dev)
{
gic_state *s = FROM_SYSBUS(gic_state, dev);
int num_irq = s->num_irq;
if (s->num_cpu > NCPU) {
hw_error("requested %u CPUs exceeds GIC maximum %d\n",
s->num_cpu, NCPU);
}
s->num_irq += GIC_BASE_IRQ;
if (s->num_irq > GIC_MAXIRQ) {
hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
num_irq, GIC_MAXIRQ);
}
/* ITLinesNumber is represented as (N / 32) - 1 (see
* gic_dist_readb) so this is an implementation imposed
* restriction, not an architectural one:
*/
if (s->num_irq < 32 || (s->num_irq % 32)) {
hw_error("%d interrupt lines unsupported: not divisible by 32\n",
num_irq);
}
register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
return 0;
}
static void arm_sysctl_finalize(Object *obj)
{
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
g_free(s->db_voltage);
g_free(s->db_clock);
g_free(s->db_clock_reset);
}
static int syborg_virtio_net_init(SysBusDevice *dev)
{
VirtIODevice *vdev;
SyborgVirtIOProxy *proxy = FROM_SYSBUS(SyborgVirtIOProxy, dev);
vdev = virtio_net_init(&dev->qdev, &proxy->nic, &proxy->net);
return syborg_virtio_init(proxy, vdev);
}
static void rotary_init(SysBusDevice *dev)
{
RotaryCoderState *s = FROM_SYSBUS(RotaryCoderState, dev);
qdev_init_gpio_out(&dev->qdev, s->out, 2);
qemu_add_kbd_event_handler(rotary_keyboard_event, s);
register_savevm("gpio_rotary", -1, 1, rotary_save, rotary_load, s);
}
static void syborg_virtio_net_init(SysBusDevice *dev)
{
VirtIODevice *vdev;
SyborgVirtIOProxy *proxy = FROM_SYSBUS(SyborgVirtIOProxy, dev);
vdev = virtio_net_init(&dev->qdev);
syborg_virtio_init(proxy, vdev);
}
/* System RAM */
static int ram_init1(SysBusDevice *dev)
{
RamDevice *d = FROM_SYSBUS(RamDevice, dev);
memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
vmstate_register_ram_global(&d->ram);
sysbus_init_mmio(dev, &d->ram);
return 0;
}
static int empty_slot_init1(SysBusDevice *dev)
{
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
memory_region_init_io(&s->iomem, &empty_slot_ops, s,
"empty-slot", s->size);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void arm_mptimer_reset(DeviceState *dev)
{
ARMMPTimerState *s =
FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev));
int i;
for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
timerblock_reset(&s->timerblock[i]);
}
}
static int imx_ccm_init(SysBusDevice *dev)
{
IMXCCMState *s = FROM_SYSBUS(typeof(*s), dev);
memory_region_init_io(&s->iomem, &imx_ccm_ops, s, "imx_ccm", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void lan9118_reset(DeviceState *d)
{
lan9118_state *s = FROM_SYSBUS(lan9118_state, SYS_BUS_DEVICE(d));
s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
s->int_sts = 0;
s->int_en = 0;
s->fifo_int = 0x48000000;
s->rx_cfg = 0;
s->tx_cfg = 0;
s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004;
s->pmt_ctrl &= 0x45;
s->gpio_cfg = 0;
s->txp->fifo_used = 0;
s->txp->state = TX_IDLE;
s->txp->cmd_a = 0xffffffffu;
s->txp->cmd_b = 0xffffffffu;
s->txp->len = 0;
s->txp->fifo_used = 0;
s->tx_fifo_size = 4608;
s->tx_status_fifo_used = 0;
s->rx_status_fifo_size = 704;
s->rx_fifo_size = 2640;
s->rx_fifo_used = 0;
s->rx_status_fifo_size = 176;
s->rx_status_fifo_used = 0;
s->rxp_offset = 0;
s->rxp_size = 0;
s->rxp_pad = 0;
s->rx_packet_size_tail = s->rx_packet_size_head;
s->rx_packet_size[s->rx_packet_size_head] = 0;
s->mac_cmd = 0;
s->mac_data = 0;
s->afc_cfg = 0;
s->e2p_cmd = 0;
s->e2p_data = 0;
s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40;
ptimer_stop(s->timer);
ptimer_set_count(s->timer, 0xffff);
s->gpt_cfg = 0xffff;
s->mac_cr = MAC_CR_PRMS;
s->mac_hashh = 0;
s->mac_hashl = 0;
s->mac_mii_acc = 0;
s->mac_mii_data = 0;
s->mac_flow = 0;
s->read_word_n = 0;
s->write_word_n = 0;
phy_reset(s);
s->eeprom_writable = 0;
lan9118_reload_eeprom(s);
}
