static int a15mp_priv_init(SysBusDevice *dev) { A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev); if (s->num_cpu > NCPU) { hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU); } gic_init(&s->gic, s->num_cpu, s->num_irq); /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved * 0x1000-0x1fff -- GIC Distributor * 0x2000-0x2fff -- GIC CPU interface * 0x4000-0x4fff -- GIC virtual interface control (not modelled) * 0x5000-0x5fff -- GIC virtual interface control (not modelled) * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) */ memory_region_init(&s->container, "a15mp-priv-container", 0x8000); memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem); memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]); sysbus_init_mmio(dev, &s->container); return 0; }
static int realview_gic_init(SysBusDevice *dev) { RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); gic_init(&s->gic); s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn, realview_gic_cpu_writefn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map); return 0; }
static int realview_gic_init(SysBusDevice *dev) { RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); /* The GICs on the RealView boards have a fixed nonconfigurable * number of interrupt lines, so we don't need to expose this as * a qdev property. */ gic_init(&s->gic, 96); realview_gic_map_setup(s); sysbus_init_mmio(dev, &s->container); return 0; }
static int exynos4210_gic_init(SysBusDevice *dev) { Exynos4210GicState *s = FROM_SYSBUSGIC(Exynos4210GicState, dev); uint32_t i; const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; const char dist_prefix[] = "exynos4210-gic-alias_dist"; char cpu_alias_name[sizeof(cpu_prefix) + 3]; char dist_alias_name[sizeof(cpu_prefix) + 3]; gic_init(&s->gic, s->num_cpu, EXYNOS4210_GIC_NIRQ); memory_region_init(&s->cpu_container, "exynos4210-cpu-container", EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); memory_region_init(&s->dist_container, "exynos4210-dist-container", EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); for (i = 0; i < s->num_cpu; i++) { /* Map CPU interface per SMP Core */ sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); memory_region_init_alias(&s->cpu_alias[i], cpu_alias_name, &s->gic.cpuiomem[0], 0, EXYNOS4210_GIC_CPU_REGION_SIZE); memory_region_add_subregion(&s->cpu_container, EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); /* Map Distributor per SMP Core */ sprintf(dist_alias_name, "%s%x", dist_prefix, i); memory_region_init_alias(&s->dist_alias[i], dist_alias_name, &s->gic.iomem, 0, EXYNOS4210_GIC_DIST_REGION_SIZE); memory_region_add_subregion(&s->dist_container, EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); } sysbus_init_mmio(dev, &s->cpu_container); sysbus_init_mmio(dev, &s->dist_container); gic_cpu_write(&s->gic, 1, 0, 1); return 0; }
static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base) { RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); cpu_register_physical_memory(base, 0x1000, s->iomemtype); cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); }