void stm32_selectlcd(void) { irqstate_t flags; int i; /* Configure LCD GPIO pis */ flags = irqsave(); for (i = 0; i < NLCD_GPIOS; i++) { stm32_configgpio(g_lcdconfig[i]); } /* Enable AHB clocking to the FSMC */ stm32_enablefsmc(); /* Bank1 NOR/SRAM control register configuration */ putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); /* Bank1 NOR/SRAM timing register configuration */ putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); putreg32(0xffffffff, STM32_FSMC_BWTR4); /* Enable the bank by setting the MBKEN bit */ putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); irqrestore(flags); }
static void stm32_selectlcd(void) { /* Configure new GPIO state */ stm32_extmemgpios(fsmc_gpios, NGPIOS); /* Enable AHB clocking to the FSMC */ stm32_enablefsmc(); /* Bank1 NOR/SRAM control register configuration */ putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); /* Bank1 NOR/SRAM timing register configuration */ putreg32( FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); /* As ext mode is not active the write timing is ignored!! */ putreg32(0xffffffff, STM32_FSMC_BWTR1); /* Enable the bank by setting the MBKEN bit */ putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); }
void stm32_selectsram(void) { /* Configure new GPIO state */ stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* Enable AHB clocking to the FSMC */ stm32_enablefsmc(); /* Bank1 NOR/SRAM control register configuration */ putreg32(FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR3); /* Bank1 NOR/SRAM timing register configuration */ putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTRUN(1)| FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3); /* Enable the bank */ putreg32(FSMC_BCR_MBKEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR3); }
void stm32_selectsram(void) { /* Configure new GPIO pins */ stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ /* Enable AHB clocking to the FSMC */ stm32_enablefsmc(); /* Bank1 NOR/SRAM control register configuration * * Bank enable : Not yet * Data address mux : Disabled * Memory Type : PSRAM * Data bus width : 16-bits * Flash access : Disabled * Burst access mode : Disabled * Polarity : Low * Wrapped burst mode : Disabled * Write timing : Before state * Write enable : Yes * Wait signal : Disabled * Extended mode : Disabled * Asynchronous wait : Disabled * Write burst : Disabled */ putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); /* Bank1 NOR/SRAM timing register configuration */ putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTRUN(SRAM_BUS_TURNAROUND_DURATION) | FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | FSMC_BTR_ACCMODA), STM32_FSMC_BTR2); /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ /* Enable the bank */ putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); }
void stm32_selectlcd(void) { /* Configure new GPIO pins */ stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ /* Enable AHB clocking to the FSMC */ stm32_enablefsmc(); /* Color LCD configuration (LCD configured as follow): * * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. * - Extended Mode = Disable "FSMC_BCR_EXTMOD" * - Memory Type = SRAM "FSMC_BCR_SRAM" * - Data Width = 16bit "FSMC_BCR_MWID16" * - Write Operation = Enable "FSMC_BCR_WREN" * - Asynchronous Wait = Disable */ /* Bank3 NOR/SRAM control register configuration */ putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); /* Bank3 NOR/SRAM timing register configuration */ putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) | FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3); /* Enable the bank by setting the MBKEN bit */ putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); }