static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
{
int i, active_slots;
u32 mask = 0;
active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
for (i = 0; i < active_slots; i++)
mask |= (1 << i);
mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* bit stream is MSB first with no delay */
/* DSP_B mode */
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
AHCLKXE);
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
else
printk(KERN_ERR "playback tdm slot %d not supported\n",
dev->tdm_slots);
mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
} else {
/* bit stream is MSB first with no delay */
/* DSP_B mode */
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
AHCLKRE);
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
else
printk(KERN_ERR "capture tdm slot %d not supported\n",
dev->tdm_slots);
mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
}
}
static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
{
int i, active_slots;
u32 mask = 0, val;
active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
for (i = 0; i < active_slots; i++)
mask |= (1 << i);
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* bit stream is MSB first with no delay */
/* DSP_B mode or I2S mode */
/* AHCLK from internal clk */
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
AHCLKXE);
/* in which tdm slots is the transmitter active */
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
/* MSB first (and 1 bit delay for I2S) */
val = TXORD;
if ((dev->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_I2S)
val |= FSXDLY(1);
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, val);
if (((dev->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_I2S) &&
(dev->tdm_slots != 2))
dev_err(dev->dev, "I2S should have 2 tdm_slots\n");
if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
else
printk(KERN_ERR "playback tdm slot %d not supported\n",
dev->tdm_slots);
/* frame sync width */
if ((dev->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_I2S)
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSXDUR);
else
mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSXDUR);
} else {
/* bit stream is MSB first (and 1 bit delay for I2S) */
/* DSP_B mode or I2S mode */
val = TXORD;
if ((dev->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_I2S)
val |= FSXDLY(1);
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, val);
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
AHCLKXE);
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
AHCLKRE);
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) {
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSRMOD(dev->tdm_slots), FSXMOD(0x1FF));
}
else
printk(KERN_ERR "capture tdm slot %d not supported\n",
dev->tdm_slots);
/* frame sync width */
if ((dev->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_I2S) {
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSXDUR);
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
FSRDUR);
}
else {
mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
FSXDUR);
mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
FSRDUR);
}
}
}
