Example #1
0
};

static struct vote_clk gcc_ce1_axi_clk = {
	.cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
	.en_mask  = BIT(4),

	.c = {
		.dbg_name = "gcc_ce1_axi_clk",
		.ops      = &clk_ops_vote,
	},
};

/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
	F_MM(19200000,    cxo,   1,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
	F_MM(19200000,    cxo,   1,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
	F_MM(19200000,     cxo,     1,   0,   0),
	F_MM(100000000,  gpll0,     6,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mdp_clk[] = {
};

static struct branch_clk gcc_usb_hs_ahb_clk =
{
	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
	.has_sibling  = 1,

	.c = {
		.dbg_name = "gcc_usb_hs_ahb_clk",
		.ops      = &clk_ops_branch,
	},
};

/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
	F_MM(19200000,    cxo,   1,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
	F_MM(19200000,    cxo,   1,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mdp_clk[] = {
	F( 80000000,  gpll0,   10,    0,    0),
	F( 100000000, gpll0,    8,    0,    0),
	F( 200000000, gpll0,    4,    0,    0),
	F( 320000000, gpll0,  2.5,    0,    0),
	F_END
};
Example #3
0
};

static struct vote_clk gcc_ce1_axi_clk = {
	.cbcr_reg     = (uint32_t *) GCC_CE1_AXI_CBCR,
	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
	.en_mask      = BIT(4),

	.c = {
		.dbg_name = "gcc_ce1_axi_clk",
		.ops      = &clk_ops_vote,
	},
};

/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
	F_MM(19200000,    cxo,   1,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
	F_MM(19200000,     cxo,     1,   0,   0),
	F_MM(100000000,  gpll0,     6,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mdp_clk[] = {
	F_MM( 75000000,  gpll0,   8,    0,    0),
	F_MM( 100000000, gpll0,   6,    0,    0),
	F_MM( 200000000, gpll0,   3,    0,    0),
	F_END
};
};

static struct branch_clk gcc_usb_hs_ahb_clk =
{
	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
	.has_sibling  = 1,

	.c = {
		.dbg_name = "gcc_usb_hs_ahb_clk",
		.ops      = &clk_ops_branch,
	},
};

/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
	F_MM(19200000,    cxo,   1,   0,   0),
	F_END
};

static struct clk_freq_tbl ftbl_mdp_clk[] = {
	F_MM( 80000000,  gpll0,   10,    0,    0),
	F_MM( 100000000, gpll0,    8,    0,    0),
	F_MM( 200000000, gpll0,    4,    0,    0),
	F_MM( 320000000, gpll0,  2.5,    0,    0),
	F_END
};

static struct rcg_clk dsi_esc0_clk_src = {
	.cmd_reg  = (uint32_t *) DSI_ESC0_CMD_RCGR,
	.cfg_reg  = (uint32_t *) DSI_ESC0_CFG_RCGR,
	.set_rate = clock_lib2_rcg_set_rate_hid,