void VideoBackend::Video_Prepare()
{
// Better be safe...
s_efbAccessRequested = FALSE;
s_FifoShuttingDown = FALSE;
s_swapRequested = FALSE;
// internal interfaces
g_vertex_manager = new VertexManager;
g_renderer = new Renderer;
g_texture_cache = new TextureCache;
// VideoCommon
BPInit();
Fifo_Init();
VertexLoaderManager::Init();
OpcodeDecoder_Init();
VertexShaderManager::Init();
PixelShaderManager::Init();
CommandProcessor::Init();
PixelEngine::Init();
DLCache::Init();
// Notify the core that the video backend is ready
Host_Message(WM_USER_CREATE);
}
void VideoBackend::Video_Prepare()
{
// Better be safe...
s_efbAccessRequested = FALSE;
s_FifoShuttingDown = FALSE;
s_swapRequested = FALSE;
// internal interfaces
g_renderer = new Renderer(m_window_handle);
g_texture_cache = new TextureCache;
g_vertex_manager = new VertexManager;
g_perf_query = new PerfQuery;
VertexShaderCache::Init();
PixelShaderCache::Init();
D3D::InitUtils();
// VideoCommon
BPInit();
Fifo_Init();
IndexGenerator::Init();
VertexLoaderManager::Init();
OpcodeDecoder_Init();
VertexShaderManager::Init();
PixelShaderManager::Init();
CommandProcessor::Init();
PixelEngine::Init();
// Tell the host that the window is ready
Host_Message(WM_USER_CREATE);
}
void VideoBackend::Video_Prepare()
{
// internal interfaces
g_renderer = new Renderer(m_window_handle);
g_texture_cache = new TextureCache;
g_vertex_manager = new VertexManager;
g_perf_query = new PerfQuery;
VertexShaderCache::Init();
PixelShaderCache::Init();
GeometryShaderCache::Init();
D3D::InitUtils();
// VideoCommon
BPInit();
Fifo_Init();
IndexGenerator::Init();
VertexLoaderManager::Init();
OpcodeDecoder_Init();
VertexShaderManager::Init();
PixelShaderManager::Init();
GeometryShaderManager::Init();
CommandProcessor::Init();
PixelEngine::Init();
BBox::Init();
// Tell the host that the window is ready
Host_Message(WM_USER_CREATE);
}
int testqueue(void){
Fifo_Init();
for(;;){
Status[0] = Fifo_Get(&GetData[0]); // should fail, empty
Status[1] = Fifo_Put(1); // should succeed, 1
Status[2] = Fifo_Put(2); // should succeed, 1 2
Status[3] = Fifo_Put(3); // should succeed, 1 2 3
Status[4] = Fifo_Put(4); // should succeed, 1 2 3 4
Status[5] = Fifo_Put(5); // should succeed, 1 2 3 4 5
Status[6] = Fifo_Put(6); // should succeed, 1 2 3 4 5 6
Status[7] = Fifo_Put(7); // should fail, 1 2 3 4 5 6
Status[8] = Fifo_Get(&GetData[1]); // should succeed, 2 3 4 5 6
Status[9] = Fifo_Get(&GetData[2]); // should succeed, 3 4 5 6
Status[10] = Fifo_Put(7); // should succeed, 3 4 5 6 7
Status[11] = Fifo_Put(8); // should succeed, 3 4 5 6 7 8
Status[12] = Fifo_Put(9); // should fail, 3 4 5 6 7 8
Status[13] = Fifo_Get(&GetData[3]); // should succeed, 4 5 6 7 8
Status[14] = Fifo_Get(&GetData[4]); // should succeed, 5 6 7 8
Status[15] = Fifo_Get(&GetData[5]); // should succeed, 6 7 8
Status[16] = Fifo_Get(&GetData[6]); // should succeed, 7 8
Status[17] = Fifo_Get(&GetData[7]); // should succeed, 8
Status[18] = Fifo_Get(&GetData[8]); // should succeed, empty
Status[19] = Fifo_Get(&GetData[9]); // should fail, empty
}
}
void main(void){
PLL_Init(); // running at 24MHz
DDRT |= 0x1F; // debugging outputs
PTT &= ~0x1F;
Debug_Profile(0); // 0 means initialization phase
Fifo_Init(); // Initialize fifo
OC0_Init(); // variable rate interrupt
ForeExpected = 0; // expected data
for(;;){
Debug_Profile(1); // 1 means start of foreground waiting
PTT_PTT1 = 0; // falling edge of PT1 means start of foreground waiting
while(Fifo_Get(&ForeData)==FIFOFAIL){
}
Debug_Profile(2); // 2 means foreground has new data
PTT_PTT1 = 1; // rising edge of PT1 means start of foreground processing
if(ForeExpected != ForeData){
Errors++;
PTT ^= 0x10; // critical section found
ForeExpected = ForeData+1; // resych to lost/bad data
}
else{
ForeExpected++; // sequence is 0,1,2,3,...,254,255,0,1,...
}
if((ForeData%10)==0){
Debug_Profile(3); // 3 means foreground has 10th data
}
}
}
// This is called after Initialize() from the Core
// Run from the graphics thread
void VideoBackend::Video_Prepare()
{
GLInterface->MakeCurrent();
g_renderer = std::make_unique<Renderer>();
CommandProcessor::Init();
PixelEngine::Init();
BPInit();
g_vertex_manager = std::make_unique<VertexManager>();
g_perf_query = GetPerfQuery();
Fifo_Init(); // must be done before OpcodeDecoder_Init()
OpcodeDecoder_Init();
IndexGenerator::Init();
VertexShaderManager::Init();
PixelShaderManager::Init();
GeometryShaderManager::Init();
ProgramShaderCache::Init();
g_texture_cache = std::make_unique<TextureCache>();
g_sampler_cache = std::make_unique<SamplerCache>();
Renderer::Init();
VertexLoaderManager::Init();
TextureConverter::Init();
BoundingBox::Init();
// Notify the core that the video backend is ready
Host_Message(WM_USER_CREATE);
}
IOLAYER *IoLayerW32_Init(void)
{
IOLAYER_INST *hIO;
if (!(hIO = calloc(1, sizeof(IOLAYER_INST))))
return NULL;
// Init Inet
if (!(hIO->hInet = InternetOpen ("Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13",
INTERNET_OPEN_TYPE_PRECONFIG, NULL, "<local>", 0)))
{
free (hIO);
return NULL;
}
if (!(hIO->hResult = Fifo_Init(1024)))
{
IoLayer_Exit((IOLAYER*)hIO);
return NULL;
}
//InternetSetCookie ("https://o.imo.im/", "proto", "prpl-skype");
// Init Vtbl
hIO->vtbl.Exit = IoLayer_Exit;
hIO->vtbl.Post = IoLayer_Post;
hIO->vtbl.Get = IoLayer_Get;
hIO->vtbl.Cancel = IoLayer_Cancel;
hIO->vtbl.GetLastError = IoLayer_GetLastError;
hIO->vtbl.EscapeString = IoLayer_EscapeString;
hIO->vtbl.FreeEscapeString = IoLayer_FreeEscapeString;
return (IOLAYER*)hIO;
}
// This is called after Initialize() from the Core
// Run from the graphics thread
void VideoBackend::Video_Prepare()
{
GLInterface->MakeCurrent();
g_renderer = new Renderer;
s_efbAccessRequested = false;
s_FifoShuttingDown = false;
s_swapRequested = false;
CommandProcessor::Init();
PixelEngine::Init();
g_texture_cache = new TextureCache;
BPInit();
g_vertex_manager = new VertexManager;
Fifo_Init(); // must be done before OpcodeDecoder_Init()
OpcodeDecoder_Init();
VertexShaderCache::Init();
VertexShaderManager::Init();
PixelShaderCache::Init();
PixelShaderManager::Init();
PostProcessing::Init();
GL_REPORT_ERRORD();
VertexLoaderManager::Init();
TextureConverter::Init();
DLCache::Init();
// Notify the core that the video backend is ready
Host_Message(WM_USER_CREATE);
}
// This is called after Initialize() from the Core
// Run from the graphics thread
void VideoBackend::Video_Prepare()
{
GLInterface->MakeCurrent();
g_renderer = new Renderer;
CommandProcessor::Init();
PixelEngine::Init();
BPInit();
g_vertex_manager = new VertexManager;
g_perf_query = new PerfQuery;
Fifo_Init(); // must be done before OpcodeDecoder_Init()
OpcodeDecoder_Init();
IndexGenerator::Init();
VertexShaderManager::Init();
PixelShaderManager::Init();
ProgramShaderCache::Init();
g_texture_cache = new TextureCache();
g_sampler_cache = new SamplerCache();
Renderer::Init();
VertexLoaderManager::Init();
TextureConverter::Init();
// Notify the core that the video backend is ready
Host_Message(WM_USER_CREATE);
}
/**
test routine
*/
IFX_void_t FifoTest(IFX_void_t)
{
IFX_uint16_t buf [3];
IFX_uint16_t tst = 1;
IFX_uint16_t *entry = IFX_NULL;
FIFO fifo;
Fifo_Init (&fifo, &buf[0], &buf[2], sizeof (IFX_uint16_t));
entry = Fifo_writeElement (&fifo);
if (entry != IFX_NULL)
*entry = 1;
entry = Fifo_writeElement (&fifo);
if (entry != IFX_NULL)
{
*entry = 2;
Fifo_returnElement (&fifo);
}
entry = Fifo_readElement (&fifo);
if (entry != IFX_NULL)
tst = *entry;
entry = Fifo_readElement (&fifo);
if (entry != IFX_NULL)
tst = *entry;
}
//------------UART_Init------------
// Wait for new serial port input
// Initialize the UART for 115,200 baud rate (assuming 50 MHz UART clock),
// 8 bit word length, no parity bits, one stop bit, FIFOs enabled
// Input: none
// Output: none
void UART1_Init(void){
Fifo_Init();
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART1; // activate UART0
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOG; // activate port G
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; // activate port D
UART1_CTL_R &= ~UART_CTL_UARTEN; // disable UART
UART1_IBRD_R = 31; // IBRD = int(50,000,000 / (16 * 100,000)) = int(31.25)
UART1_FBRD_R = 16; // FBRD = int(0.25 * 64 + 0.5) = 16
// 8 bit word length (no parity bits, one stop bit, FIFOs)
UART1_LCRH_R = (UART_LCRH_WLEN_8|UART_LCRH_FEN);
UART1_IFLS_R = UART_IFLS_RX4_8;
UART1_IM_R |= UART_IM_RXIM;
NVIC_PRI1_R = (NVIC_PRI1_R & 0xFF1FFFFF) | 0x00200000;
NVIC_EN0_R |= NVIC_EN0_INT6;
UART1_CTL_R |= UART_CTL_UARTEN; // enable UART
GPIO_PORTD_AFSEL_R |= 0x0C; // enable alt funct on PD3-2
GPIO_PORTD_DEN_R |= 0x0C; // enable digital I/O on PD3-2
GPIO_PORTG_DIR_R |= 0x04; // make PG2 out
GPIO_PORTG_AFSEL_R &= ~0x04;
GPIO_PORTG_PUR_R |= 0x04;
GPIO_PORTG_DEN_R |= 0x04; // enable digital I/O on PG2
GPIO_PORTG_DATA_R |= 0x04;
EnableInterrupts();
}
void main(void){
unsigned short First;
unsigned short Delay = 0;
EnableInterrupts;
PLL_Init(); // running at 24MHz
DDRT = 0xff; // debugging outputs
PTT = 0x00;
SCI0_Init(115200); // fastest standard baud rate on run mode 9S12DP512
SCI0_OutString("EE445L Lab2g -JWV"); OutCRLF();
TSCR1 = 0x80; // Enable TCNT, 24MHz assuming PLL is active
TSCR2 = 0;
// calibration offset
First = TCNT;
//nothing here
Delay = TCNT - First - 9;
SCI0_OutString("Time to execute nothing ");
SCI0_OutUDec(Delay);
SCI0_OutString(" cycles"); OutCRLF();
// measurement version 1, no debugging instruments
Fifo_Init(); // Initialize fifo
Fifo_Put(1); // make sure there is something in the fifo
First = TCNT;
Fifo_Get(&ForeData);
Delay = TCNT-First-9;
SCI0_OutString("Time to execute Fifo_Get with no debugging instruments is ");
SCI0_OutUDec(Delay);
SCI0_OutString(" cycles"); OutCRLF();
// measurement version 2, print debugging instruments
/* Fifo_Init(); // Initialize fifo
Fifo_Put(1); // make sure there is something in the fifo
First = TCNT;
Fifo_Get2(&ForeData);
Delay = TCNT-First-9;
SCI0_OutString("Time to execute Fifo_Get2 with print debugging instruments is ");
SCI0_OutUDec(Delay);
SCI0_OutString(" cycles"); OutCRLF();
// measurement version 3, dump debugging instruments
Fifo_Init(); // Initialize fifo
Fifo_Put(1); // make sure there is something in the fifo
First = TCNT;
Fifo_Get3(&ForeData);
Delay = TCNT-First-9;
SCI0_OutString("Time to execute Fifo_Get3 with dump debugging instruments is ");
SCI0_OutUDec(Delay);
SCI0_OutString(" cycles"); OutCRLF();*/
for(;;){}
}
void UART1_Handler(void){unsigned char read; unsigned char i;
Fifo_Init();
PF2 ^=0x04; //toggle heartbeat twice
PF2 ^=0x04;
while((UART1_FR_R&0x0010)!=0){}; //wait until RXFE is 0
for(i=0;i<8;i++){
read = UART1_DR_R&0xFF; //get byte information into read
if(Fifo_Put(read)==0)
error++;
}
RxCounter++;
UART1_ICR_R=0x10; //clear RXRIS in the RIS register
PF2 ^=0x04;
}
// main program for Procedure part D
void main2(void){
dataType data;
DDRT |= 0x01;
Fifo_Init(); // initialize
TSCR1 = 0x80; // Enable TCNT, 24MHz assumming PLL is active
First = TCNT;
Delay = TCNT-First;
asm cli
for(;;){
Fifo_Put(1);
PTT_PTT0 = 1;
Fifo_Get(&data);
PTT_PTT0 = 0;
}
}
static char *IoLayer_EscapeString(IOLAYER *hPIO, char *pszData)
{
IOLAYER_INST *hIO = (IOLAYER_INST*)hPIO;
TYP_FIFO *hFifo;
char szBuf[8], *pszRet;
unsigned char *p;
if (!(hFifo = Fifo_Init(strlen(pszData)))) return NULL;
for (p=pszData; *p; p++)
{
if (isalnum(*p)) Fifo_Add (hFifo, p, 1);
else {
wsprintf (szBuf, "%%%02X", *p);
Fifo_Add (hFifo, szBuf, 3);
}
}
Fifo_Add (hFifo, "", 1);
if (pszRet = Fifo_Get(hFifo, NULL))
pszRet = strdup(pszRet);
Fifo_Exit(hFifo);
return pszRet;
}
void UART1_Init(void){
Fifo_Init();
SYSCTL_RCGC1_R |= 0x0002; //activate UART1
SYSCTL_RCGC2_R |= 0x0004; //activate PortC
UART1_CTL_R &= ~0x001; //disable UART during init
UART1_IBRD_R = 50; //bit rate=(80000000/16*100000)=50
UART1_FBRD_R = 0;
UART1_LCRH_R = 0x0070; //8-bit word length, enable FIFO
//enable interrups
UART1_IM_R |= 0x10; //set RXIM interrupt mask
UART1_IFLS_R &= 0xFFFFFFD7; //clear bits 5 and 3 of IFLS
UART1_IFLS_R |= 0x10; //set bit 4 to enable interrupts
//set interrupr priority
NVIC_PRI1_R = (NVIC_PRI1_R & 0xFF00FFFF)|0x00400000; //Priotity 2
NVIC_EN0_R |= 0x40; //priority for UART1
//enable UART
UART1_CTL_R = 0x0301; //enable RXE, TXE and UART
GPIO_PORTC_PCTL_R = (GPIO_PORTC_PCTL_R&0xFF00FFFF)+0x00220000; //write 2
GPIO_PORTC_AMSEL_R &= ~0x30; //disable PC4,5 analog funtion
GPIO_PORTC_AFSEL_R |= 0x30; //enable PC4,5 alt function
GPIO_PORTC_DEN_R |= 0x30; //enable PC4,5 digital I/O
}
int
main(int argc, char* argv[])
{
volatile FATFS fatfs = {0};
volatile FRESULT result;
uint8_t fifo_command = 0;
uint8_t file_index = 0;
ResetRCC();
RCC_SetClockFrequency(PLLM_macro, PLLN_macro, PLLQ_macro, PLLP_macro);
// Enable clocks for the peripherals
/*
* GPIOA - NEC_CONTROLLER, TIM1 PWM, DAC
* GPIOB - SPI2
* GPIOC - HD44780 Led Display
* GPIOD - LED diodes, USART2(Log)
*/
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN;
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
RCC->APB1ENR |= RCC_APB1ENR_TIM7EN | RCC_APB1ENR_SPI2EN | RCC_APB1ENR_USART2EN | RCC_APB1ENR_DACEN;
/*< Configure board's leds to signal states */
GPIO_OutputConfigure(GPIOD, PIN_12 | PIN_13 | PIN_14 | PIN_15, gpio_otyper_push_pull, gpio_speed_high, gpio_pupd_pull_down);
/*< Configure NVIC Interrupt controller */
// Set two bits (out of four) as the main priority. The rest bits are used for preemptive priorities
NVIC_SetPriorityGrouping(NVIC_PriorityGroup_2);
NVIC_Enable_Interrupts();
/*< Configure USART2 module to create program log */
UART_Config(USART2, USART_CR1_UE | USART_CR1_TE, 19200,false);
GPIO_AlternateFunctionPrepare(GPIOD, PIN_5, gpio_otyper_push_pull, gpio_speed_medium, gpio_pupd_pull_up);
GPIO_AlternateFunctionSet(GPIOD,PIN_5, AF7);
Log_Uart("##### LOG START #####\n\r");
/*< MCO2 Pin configuration to watch the CPU Clock signal with an oscilloscope*/
Log_Uart("Clock output pin configuration in progress...\n\r");
RCC->CFGR |= RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1;
RCC->CFGR &= ~RCC_CFGR_MCO2;
GPIO_AlternateFunctionPrepare(GPIOC, PIN_9, gpio_otyper_push_pull, gpio_speed_fast, gpio_pupd_no_pull);
GPIO_AlternateFunctionSet(GPIOC,PIN_9, AF0);
/*< SysTick configuration */
Log_Uart("SysTick configuration in progress...\n\r");
SysTick_Config(SYSTICK_CLK_DIVIDER); // Configure SysTick to make a tick every 1 us
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
/*< PWM signal configuration */
Log_Uart("PWM generation module configuration in progress...\n\r");
GPIO_AlternateFunctionPrepare(GPIOA, PIN_8, gpio_otyper_push_pull, gpio_speed_fast, gpio_pupd_pull_down);
GPIO_AlternateFunctionSet(GPIOA, PIN_8, AF1); // Pin for PWM signal
TIM_PWMConfigure(TIM1, 168, 5000, 4000, TIM_Channel_1);
TIM_Start(TIM1);
/*< HD44780 display configuration */
LCD_Config();
/*< Remote controller receiver initialization */
Log_Uart("IR remote controller configuration in progress...\n\r");
NEC_Remote_Init();
TIM_Start(TIM6);
/*< SPI Module configuration. It is used to communicate with the SD card */
Log_Uart("SPI module configuration in progress...\n\r");
SPI_Master_Init(SPI2, SPI_FREQ_PCLK_DIV_256, SPI_CPOL0_CPHA0, SPI_BIT_ORDER_MSB_FIRST, true);
/*< DAC configuration */
DAC_Init(dac_dual_channel_simultanous, dac_trigger_tim7, true);
/*< Timer 7 used to trigger the DAC config */
TIM_Basic_Continuous_Counting(TIM7, 12);
/*< Remote Controller command fifo configuration */
Log_Uart("FIFO configuration in progress...\n\r");
Fifo_Init(&remote_command_fifo, remote_command_queue, sizeof(remote_command_queue));
TIM6->CR1 |= TIM_CR1_CEN; /*< Continuously ticking timer, used in NEC IR remote */
Log_Uart("Configuration OK!\n\r");
TCHAR disk[] = "0";
UINT byte_number;
result = f_mount(&fatfs, disk, 1);
uint16_t bytes;
/* result = SD_Find_File_Name_Containing("/", "*.wav");
result = SD_Get_File_List("/");
result = f_open(&sd_current_file, &sd_files_list[3], FA_READ);
result = Wav_Get_File_Header(&sd_current_file);
*/
// Initially, get the files list
state = STATE_GET_FILES_LIST;
while(1)
{
switch(state)
{
/* case STATE_WAIT:
break;*/
case STATE_GET_FILES_LIST:
{
result = SD_Find_File_Name_Containing("/", "*.wav");
if(result == FR_NO_FILE)
{
LCD_WriteText("Brak plikow .wav");
// Go to sleep in this case
while(1)
{
__WFI();
}
}
else
{
LCD_WriteText(sd_files_list[0]);
}
state = STATE_EXECUTE_USER_REQUESTS;
break;
}
case STATE_READ_SAMPLES:
{
// If we didn't get to the end of file yet...
if(!f_eof(&sd_current_file))
// ... Then read next sample chunk
f_read(&sd_current_file, empty_data_buf_ptr, 512, &read_data_byte_counter);
else
// ... Else set the end of file flag
wav_eof = true;
state = STATE_EXECUTE_USER_REQUESTS;
break;
}
case STATE_EXECUTE_USER_REQUESTS:
{
do
{
Fifo_Get(&remote_command_fifo, &fifo_command);
switch(fifo_command)
{
case NEC_CH_PLUS:
{
// Disable when the wav_file is currently played
if(!wav_file_playing)
{
wav_file_chosen = false;
if(file_index < sd_number_of_files_in_dir-1)
file_index++;
LCD_WriteText(sd_files_list[file_index]);
}
break;
}
case NEC_CH_MINUS:
{
// Disable when the wav_file is currently played
if(!wav_file_playing)
{
wav_file_chosen = false;
if(file_index > 0)
file_index--;
LCD_WriteText(sd_files_list[file_index]);
}
break;
}
case NEC_CH:
{
// Disable when the wav_file is currently played
if(!wav_file_chosen)
{
// If the file is already opened then close it
if(sd_current_file.fs != 0)
f_close(&sd_current_file);
// ...Open the chosen file
f_open(&sd_current_file, sd_files_list[file_index], FA_READ);
// Get the chosen files header
WAV_Get_File_Header(&sd_current_file);
// Prepare the triggering timer frequency
// WAV_Set_Trigger_Frequency(TIM7);
TIM_Set_Timer_Max_Count(TIM7, (uint16_t)(TIM7_FREQ/current_wave_header.byte_field.sample_rate));
// Get the rest audio file info
//f_read(&sd_current_file, sd_data_buffer, current_wave_header.byte_field.subchunk_2_size, &read_data_byte_counter);
// Get the first portion of data
// Set the wav_file_chosen flag
wav_file_chosen = true;
// Clear the wav_eof flag
wav_eof = false;
}
break;
}
case NEC_PLAY_PAUSE:
{
if(!wav_file_playing && wav_file_chosen)
{
// Clear the timer's counter
TIM_Clear(TIM7);
TIM7->DIER |= TIM_DIER_UIE;
empty_data_buf_ptr = sd_data_buffer;
f_read(&sd_current_file, sd_data_buffer, sizeof(sd_data_buffer), &read_data_byte_counter);
f_read(&sd_current_file, sd_data_buffer_additional, sizeof(sd_data_buffer_additional), &read_data_byte_counter);
// Start the DAC triggering timer
TIM_Start(TIM7);
// Set the wav_file_playing_flag
wav_file_playing = true;
}
else
{
// Stop the DAC triggering timer
TIM_Stop(TIM7);
// Clear the wav_file_playing_ flag
wav_file_playing = false;
}
break;
}
default:
break;
}
fifo_command = 0;
}while(!Fifo_Empty(&remote_command_fifo));
break;
}
}
}
}
void RecibirDato(void){
// sendChar(dato);
switch (status){
case IDLE:
if(dato==MOTOR_ID){
status=SELECTED;
}
break;
case SELECTED:
if(Fifo_Put(dato)){
if(dato==READMOT){ //SENSE QUESTION
//queue enable variator response bit and timer at rx complete
j=1;
//status=RX;
}else if(dato==CR){
status=IDLE;
ENABLE_INT_TX();
}
}else{
Fifo_Init();
status=IDLE;
}
break;
/* case RX:
//FEED FIFO
if(Fifo_Put(dato)){
if(dato==CR){
status=IDLE;
ENABLE_INT_TX();
}
}else{
Fifo_Init();
status=IDLE;
}
break; */
default:
break;
}
}
