/**Function*************************************************************
Synopsis [Returns 1 if the node is the root of MUX or EXOR/NEXOR.]
Description [The node can be complemented.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_NodeIsMuxType( Fraig_Node_t * pNode )
{
Fraig_Node_t * pNode1, * pNode2;
// make the node regular (it does not matter for EXOR/NEXOR)
pNode = Fraig_Regular(pNode);
// if the node or its children are not ANDs or not compl, this cannot be EXOR type
if ( !Fraig_NodeIsAnd(pNode) )
return 0;
if ( !Fraig_NodeIsAnd(pNode->p1) || !Fraig_IsComplement(pNode->p1) )
return 0;
if ( !Fraig_NodeIsAnd(pNode->p2) || !Fraig_IsComplement(pNode->p2) )
return 0;
// get children
pNode1 = Fraig_Regular(pNode->p1);
pNode2 = Fraig_Regular(pNode->p2);
assert( pNode1->Num < pNode2->Num );
// compare grandchildren
// node is an EXOR/NEXOR
if ( pNode1->p1 == Fraig_Not(pNode2->p1) && pNode1->p2 == Fraig_Not(pNode2->p2) )
return 1;
// otherwise the node is MUX iff it has a pair of equal grandchildren
return pNode1->p1 == Fraig_Not(pNode2->p1) ||
pNode1->p1 == Fraig_Not(pNode2->p2) ||
pNode1->p2 == Fraig_Not(pNode2->p1) ||
pNode1->p2 == Fraig_Not(pNode2->p2);
}
/**Function*************************************************************
Synopsis [Prints the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_PrintNode( Fraig_Man_t * p, Fraig_Node_t * pNode )
{
Fraig_NodeVec_t * vNodes;
Fraig_Node_t * pTemp;
int fCompl1, fCompl2, i;
vNodes = Fraig_DfsOne( p, pNode, 0 );
for ( i = 0; i < vNodes->nSize; i++ )
{
pTemp = vNodes->pArray[i];
if ( Fraig_NodeIsVar(pTemp) )
{
printf( "%3d : PI ", pTemp->Num );
Fraig_PrintBinary( stdout, (unsigned *)&pTemp->puSimR, 20 );
printf( " " );
Fraig_PrintBinary( stdout, (unsigned *)&pTemp->puSimD, 20 );
printf( " %d\n", pTemp->fInv );
continue;
}
fCompl1 = Fraig_IsComplement(pTemp->p1);
fCompl2 = Fraig_IsComplement(pTemp->p2);
printf( "%3d : %c%3d %c%3d ", pTemp->Num,
(fCompl1? '-':'+'), Fraig_Regular(pTemp->p1)->Num,
(fCompl2? '-':'+'), Fraig_Regular(pTemp->p2)->Num );
Fraig_PrintBinary( stdout, (unsigned *)&pTemp->puSimR, 20 );
printf( " " );
Fraig_PrintBinary( stdout, (unsigned *)&pTemp->puSimD, 20 );
printf( " %d\n", pTemp->fInv );
}
Fraig_NodeVecFree( vNodes );
}
/**Function*************************************************************
Synopsis [Prepares the SAT solver to run on the two nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_PrepareCones( Fraig_Man_t * pMan, Fraig_Node_t * pOld, Fraig_Node_t * pNew )
{
// Msat_IntVec_t * vAdjs;
// int * pVars, nVars, i, k;
int nVarsAlloc;
assert( pOld != pNew );
assert( !Fraig_IsComplement(pOld) );
assert( !Fraig_IsComplement(pNew) );
// clean the variables
nVarsAlloc = Msat_IntVecReadSize(pMan->vVarsUsed);
Msat_IntVecFill( pMan->vVarsUsed, nVarsAlloc, 0 );
Msat_IntVecClear( pMan->vVarsInt );
pMan->nTravIds++;
Fraig_PrepareCones_rec( pMan, pNew );
Fraig_PrepareCones_rec( pMan, pOld );
/*
nVars = Msat_IntVecReadSize( pMan->vVarsInt );
pVars = Msat_IntVecReadArray( pMan->vVarsInt );
for ( i = 0; i < nVars; i++ )
{
// process its connections
vAdjs = (Msat_IntVec_t *)Msat_ClauseVecReadEntry( pMan->vAdjacents, pVars[i] );
printf( "%d=%d { ", pVars[i], Msat_IntVecReadSize(vAdjs) );
for ( k = 0; k < Msat_IntVecReadSize(vAdjs); k++ )
printf( "%d ", Msat_IntVecReadEntry(vAdjs,k) );
printf( "}\n" );
}
i = 0;
*/
}
/**Function*************************************************************
Synopsis [Returns 1 if pOld is in the TFI of pNew.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_CheckTfi( Fraig_Man_t * pMan, Fraig_Node_t * pOld, Fraig_Node_t * pNew )
{
assert( !Fraig_IsComplement(pOld) );
assert( !Fraig_IsComplement(pNew) );
pMan->nTravIds++;
return Fraig_CheckTfi_rec( pMan, pNew, pOld );
}
/**Function*************************************************************
Synopsis [Returns 1 if the node is EXOR, 0 if it is NEXOR.]
Description [The node should be EXOR type and not complemented.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_NodeIsExor( Fraig_Node_t * pNode )
{
Fraig_Node_t * pNode1;
assert( !Fraig_IsComplement(pNode) );
assert( Fraig_NodeIsExorType(pNode) );
assert( Fraig_IsComplement(pNode->p1) );
// get children
pNode1 = Fraig_Regular(pNode->p1);
return Fraig_IsComplement(pNode1->p1) == Fraig_IsComplement(pNode1->p2);
}
/**Function*************************************************************
Synopsis [Returns 1 if A v B is always true based on the siminfo.]
Description [A v B is always true iff A' * B' is always false.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_ManCheckClauseUsingSimInfo( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2 )
{
int fCompl1, fCompl2, i;
fCompl1 = 1 ^ Fraig_IsComplement(pNode1) ^ Fraig_Regular(pNode1)->fInv;
fCompl2 = 1 ^ Fraig_IsComplement(pNode2) ^ Fraig_Regular(pNode2)->fInv;
pNode1 = Fraig_Regular(pNode1);
pNode2 = Fraig_Regular(pNode2);
assert( pNode1 != pNode2 );
// check the simulation info
if ( fCompl1 && fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( ~pNode1->puSimR[i] & ~pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( ~pNode1->puSimD[i] & ~pNode2->puSimD[i] )
return 0;
return 1;
}
if ( !fCompl1 && fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( pNode1->puSimR[i] & ~pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( pNode1->puSimD[i] & ~pNode2->puSimD[i] )
return 0;
return 1;
}
if ( fCompl1 && !fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( ~pNode1->puSimR[i] & pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( ~pNode1->puSimD[i] & pNode2->puSimD[i] )
return 0;
return 1;
}
// if ( fCompl1 && fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( pNode1->puSimR[i] & pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( pNode1->puSimD[i] & pNode2->puSimD[i] )
return 0;
return 1;
}
}
/**Function*************************************************************
Synopsis [Tries to prove the final miter.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_ManProveMiter( Fraig_Man_t * p )
{
Fraig_Node_t * pNode;
int i, clk;
if ( !p->fTryProve )
return;
clk = clock();
// consider all outputs of the multi-output miter
for ( i = 0; i < p->vOutputs->nSize; i++ )
{
pNode = Fraig_Regular(p->vOutputs->pArray[i]);
// skip already constant nodes
if ( pNode == p->pConst1 )
continue;
// skip nodes that are different according to simulation
if ( !Fraig_CompareSimInfo( pNode, p->pConst1, p->nWordsRand, 1 ) )
continue;
if ( Fraig_NodeIsEquivalent( p, p->pConst1, pNode, -1, p->nSeconds ) )
{
if ( Fraig_IsComplement(p->vOutputs->pArray[i]) ^ Fraig_NodeComparePhase(p->pConst1, pNode) )
p->vOutputs->pArray[i] = Fraig_Not(p->pConst1);
else
p->vOutputs->pArray[i] = p->pConst1;
}
}
if ( p->fVerboseP )
{
// PRT( "Final miter proof time", clock() - clk );
}
}
/**Function*************************************************************
Synopsis [Analyses choice nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_MappingUpdateLevel_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode, int fMaximum )
{
Fraig_Node_t * pTemp;
int Level1, Level2, LevelE;
assert( !Fraig_IsComplement(pNode) );
if ( !Fraig_NodeIsAnd(pNode) )
return pNode->Level;
// skip the visited node
if ( pNode->TravId == pMan->nTravIds )
return pNode->Level;
pNode->TravId = pMan->nTravIds;
// compute levels of the children nodes
Level1 = Fraig_MappingUpdateLevel_rec( pMan, Fraig_Regular(pNode->p1), fMaximum );
Level2 = Fraig_MappingUpdateLevel_rec( pMan, Fraig_Regular(pNode->p2), fMaximum );
pNode->Level = 1 + Abc_MaxInt( Level1, Level2 );
if ( pNode->pNextE )
{
LevelE = Fraig_MappingUpdateLevel_rec( pMan, pNode->pNextE, fMaximum );
if ( fMaximum )
{
if ( pNode->Level < LevelE )
pNode->Level = LevelE;
}
else
{
if ( pNode->Level > LevelE )
pNode->Level = LevelE;
}
// set the level of all equivalent nodes to be the same minimum
if ( pNode->pRepr == NULL ) // the primary node
for ( pTemp = pNode->pNextE; pTemp; pTemp = pTemp->pNextE )
pTemp->Level = pNode->Level;
}
return pNode->Level;
}
/**Function*************************************************************
Synopsis [Adds clauses to the solver.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_SupergateAddClauses( Fraig_Man_t * p, Fraig_Node_t * pNode, Fraig_NodeVec_t * vSuper )
{
int fComp1, RetValue, nVars, Var, Var1, i;
assert( Fraig_NodeIsAnd( pNode ) );
nVars = Msat_SolverReadVarNum(p->pSat);
Var = pNode->Num;
assert( Var < nVars );
for ( i = 0; i < vSuper->nSize; i++ )
{
// get the predecessor nodes
// get the complemented attributes of the nodes
fComp1 = Fraig_IsComplement(vSuper->pArray[i]);
// determine the variable numbers
Var1 = Fraig_Regular(vSuper->pArray[i])->Num;
// check that the variables are in the SAT manager
assert( Var1 < nVars );
// suppose the AND-gate is A * B = C
// add !A => !C or A + !C
// fprintf( pFile, "%d %d 0%c", Var1, -Var, 10 );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(Var1, fComp1) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(Var, 1) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
}
// add A & B => C or !A + !B + C
// fprintf( pFile, "%d %d %d 0%c", -Var1, -Var2, Var, 10 );
Msat_IntVecClear( p->vProj );
for ( i = 0; i < vSuper->nSize; i++ )
{
// get the predecessor nodes
// get the complemented attributes of the nodes
fComp1 = Fraig_IsComplement(vSuper->pArray[i]);
// determine the variable numbers
Var1 = Fraig_Regular(vSuper->pArray[i])->Num;
// add this variable to the array
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(Var1, !fComp1) );
}
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(Var, 0) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
}
/**Function*************************************************************
Synopsis [Returns 1 if the node is the root of EXOR/NEXOR gate.]
Description [The node can be complemented.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_NodeIsExorType( Fraig_Node_t * pNode )
{
Fraig_Node_t * pNode1, * pNode2;
// make the node regular (it does not matter for EXOR/NEXOR)
pNode = Fraig_Regular(pNode);
// if the node or its children are not ANDs or not compl, this cannot be EXOR type
if ( !Fraig_NodeIsAnd(pNode) )
return 0;
if ( !Fraig_NodeIsAnd(pNode->p1) || !Fraig_IsComplement(pNode->p1) )
return 0;
if ( !Fraig_NodeIsAnd(pNode->p2) || !Fraig_IsComplement(pNode->p2) )
return 0;
// get children
pNode1 = Fraig_Regular(pNode->p1);
pNode2 = Fraig_Regular(pNode->p2);
assert( pNode1->Num < pNode2->Num );
// compare grandchildren
return pNode1->p1 == Fraig_Not(pNode2->p1) && pNode1->p2 == Fraig_Not(pNode2->p2);
}
/**Function*************************************************************
Synopsis [Transfers fanout to a different node.]
Description [Assumes that the other node currently has no fanouts.]
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_NodeTransferFanout( Fraig_Node_t * pNodeFrom, Fraig_Node_t * pNodeTo )
{
Fraig_Node_t * pFanout;
assert( pNodeTo->pFanPivot == NULL );
assert( pNodeTo->pFanFanin1 == NULL );
assert( pNodeTo->pFanFanin2 == NULL );
// go through the fanouts and update their fanins
Fraig_NodeForEachFanout( pNodeFrom, pFanout )
{
if ( Fraig_Regular(pFanout->p1) == pNodeFrom )
pFanout->p1 = Fraig_NotCond( pNodeTo, Fraig_IsComplement(pFanout->p1) );
else if ( Fraig_Regular(pFanout->p2) == pNodeFrom )
pFanout->p2 = Fraig_NotCond( pNodeTo, Fraig_IsComplement(pFanout->p2) );
}
// move the pointers
pNodeTo->pFanPivot = pNodeFrom->pFanPivot;
pNodeTo->pFanFanin1 = pNodeFrom->pFanFanin1;
pNodeTo->pFanFanin2 = pNodeFrom->pFanFanin2;
pNodeFrom->pFanPivot = NULL;
pNodeFrom->pFanFanin1 = NULL;
pNodeFrom->pFanFanin2 = NULL;
}
/**Function*************************************************************
Synopsis [Returns the array of nodes to be combined into one multi-input AND-gate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_CollectSupergate_rec( Fraig_Node_t * pNode, Fraig_NodeVec_t * vSuper, int fFirst, int fStopAtMux )
{
// if the new node is complemented or a PI, another gate begins
// if ( Fraig_IsComplement(pNode) || Fraig_NodeIsVar(pNode) || Fraig_NodeIsMuxType(pNode) )
if ( (!fFirst && Fraig_Regular(pNode)->nRefs > 1) ||
Fraig_IsComplement(pNode) || Fraig_NodeIsVar(pNode) ||
(fStopAtMux && Fraig_NodeIsMuxType(pNode)) )
{
Fraig_NodeVecPushUnique( vSuper, pNode );
return;
}
// go through the branches
Fraig_CollectSupergate_rec( pNode->p1, vSuper, 0, fStopAtMux );
Fraig_CollectSupergate_rec( pNode->p2, vSuper, 0, fStopAtMux );
}
/**Function*************************************************************
Synopsis [Checks if pNew exists among the implication fanins of pOld.]
Description [If pNew is an implication fanin of pOld, returns 1.
If Fraig_Not(pNew) is an implication fanin of pOld, return -1.
Otherwise returns 0.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_NodeIsInSupergate( Fraig_Node_t * pOld, Fraig_Node_t * pNew )
{
int RetValue1, RetValue2;
if ( Fraig_Regular(pOld) == Fraig_Regular(pNew) )
return (pOld == pNew)? 1 : -1;
if ( Fraig_IsComplement(pOld) || Fraig_NodeIsVar(pOld) )
return 0;
RetValue1 = Fraig_NodeIsInSupergate( pOld->p1, pNew );
RetValue2 = Fraig_NodeIsInSupergate( pOld->p2, pNew );
if ( RetValue1 == -1 || RetValue2 == -1 )
return -1;
if ( RetValue1 == 1 || RetValue2 == 1 )
return 1;
return 0;
}
/**Function*************************************************************
Synopsis [Recursively computes the DFS ordering of the nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_Dfs_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode, Fraig_NodeVec_t * vNodes, int fEquiv )
{
assert( !Fraig_IsComplement(pNode) );
// skip the visited node
if ( pNode->TravId == pMan->nTravIds )
return;
pNode->TravId = pMan->nTravIds;
// visit the transitive fanin
if ( Fraig_NodeIsAnd(pNode) )
{
Fraig_Dfs_rec( pMan, Fraig_Regular(pNode->p1), vNodes, fEquiv );
Fraig_Dfs_rec( pMan, Fraig_Regular(pNode->p2), vNodes, fEquiv );
}
if ( fEquiv && pNode->pNextE )
Fraig_Dfs_rec( pMan, pNode->pNextE, vNodes, fEquiv );
// save the node
Fraig_NodeVecPush( vNodes, pNode );
}
/**Function*************************************************************
Synopsis [Adds clauses to the solver.]
Description [This procedure is used to add external clauses to the solver.
The clauses are given by sets of nodes. Each node stands for one literal.
If the node is complemented, the literal is negated.]
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_ManAddClause( Fraig_Man_t * p, Fraig_Node_t ** ppNodes, int nNodes )
{
Fraig_Node_t * pNode;
int i, fComp, RetValue;
if ( p->pSat == NULL )
Fraig_ManCreateSolver( p );
// create four clauses
Msat_IntVecClear( p->vProj );
for ( i = 0; i < nNodes; i++ )
{
pNode = Fraig_Regular(ppNodes[i]);
fComp = Fraig_IsComplement(ppNodes[i]);
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode->Num, fComp) );
// printf( "%d(%d) ", pNode->Num, fComp );
}
// printf( "\n" );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
}
/**Function*************************************************************
Synopsis [Adds clauses to the solver.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_SupergateAddClausesExor( Fraig_Man_t * p, Fraig_Node_t * pNode )
{
Fraig_Node_t * pNode1, * pNode2;
int fComp, RetValue;
assert( !Fraig_IsComplement( pNode ) );
assert( Fraig_NodeIsExorType( pNode ) );
// get nodes
pNode1 = Fraig_Regular(Fraig_Regular(pNode->p1)->p1);
pNode2 = Fraig_Regular(Fraig_Regular(pNode->p1)->p2);
// get the complemented attribute of the EXOR/NEXOR gate
fComp = Fraig_NodeIsExor( pNode ); // 1 if EXOR, 0 if NEXOR
// create four clauses
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode->Num, fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1->Num, fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2->Num, fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode->Num, fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1->Num, !fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2->Num, !fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode->Num, !fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1->Num, fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2->Num, !fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode->Num, !fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1->Num, !fComp) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2->Num, fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
}
/**Function*************************************************************
Synopsis [Traverses the cone, collects the numbers and adds the clauses.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_PrepareCones_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
{
Fraig_Node_t * pFanin;
Msat_IntVec_t * vAdjs;
int fUseMuxes = 1, i;
int fItIsTime;
// skip if the node is aleady visited
assert( !Fraig_IsComplement(pNode) );
if ( pNode->TravId == pMan->nTravIds )
return;
pNode->TravId = pMan->nTravIds;
// collect the node's number (closer to reverse topological order)
Msat_IntVecPush( pMan->vVarsInt, pNode->Num );
Msat_IntVecWriteEntry( pMan->vVarsUsed, pNode->Num, 1 );
if ( !Fraig_NodeIsAnd( pNode ) )
return;
// if the node does not have fanins, create them
fItIsTime = 0;
if ( pNode->vFanins == NULL )
{
fItIsTime = 1;
// create the fanins of the supergate
assert( pNode->fClauses == 0 );
if ( fUseMuxes && Fraig_NodeIsMuxType(pNode) )
{
pNode->vFanins = Fraig_NodeVecAlloc( 4 );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p1)->p1) );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p1)->p2) );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p2)->p1) );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p2)->p2) );
Fraig_SupergateAddClausesMux( pMan, pNode );
}
else
{
pNode->vFanins = Fraig_CollectSupergate( pNode, fUseMuxes );
Fraig_SupergateAddClauses( pMan, pNode, pNode->vFanins );
}
assert( pNode->vFanins->nSize > 1 );
pNode->fClauses = 1;
pMan->nVarsClauses++;
// add fanins
vAdjs = (Msat_IntVec_t *)Msat_ClauseVecReadEntry( pMan->vAdjacents, pNode->Num );
assert( Msat_IntVecReadSize( vAdjs ) == 0 );
for ( i = 0; i < pNode->vFanins->nSize; i++ )
{
pFanin = Fraig_Regular(pNode->vFanins->pArray[i]);
Msat_IntVecPush( vAdjs, pFanin->Num );
}
}
// recursively visit the fanins
for ( i = 0; i < pNode->vFanins->nSize; i++ )
Fraig_PrepareCones_rec( pMan, Fraig_Regular(pNode->vFanins->pArray[i]) );
if ( fItIsTime )
{
// recursively visit the fanins
for ( i = 0; i < pNode->vFanins->nSize; i++ )
{
pFanin = Fraig_Regular(pNode->vFanins->pArray[i]);
vAdjs = (Msat_IntVec_t *)Msat_ClauseVecReadEntry( pMan->vAdjacents, pFanin->Num );
Msat_IntVecPush( vAdjs, pNode->Num );
}
}
}
int Fraig_NodeComparePhase( Fraig_Node_t * p1, Fraig_Node_t * p2 ) { assert( !Fraig_IsComplement(p1) ); assert( !Fraig_IsComplement(p2) ); return p1->fInv ^ p2->fInv; }
/**Function*************************************************************
Synopsis [Collect variables using their proximity from the nodes.]
Description [This procedure creates a variable order based on collecting
first the nodes that are the closest to the given two target nodes.]
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_OrderVariables( Fraig_Man_t * pMan, Fraig_Node_t * pOld, Fraig_Node_t * pNew )
{
Fraig_Node_t * pNode, * pFanin;
int i, k, Number, fUseMuxes = 1;
int nVarsAlloc;
assert( pOld != pNew );
assert( !Fraig_IsComplement(pOld) );
assert( !Fraig_IsComplement(pNew) );
pMan->nTravIds++;
// clean the variables
nVarsAlloc = Msat_IntVecReadSize(pMan->vVarsUsed);
Msat_IntVecFill( pMan->vVarsUsed, nVarsAlloc, 0 );
Msat_IntVecClear( pMan->vVarsInt );
// add the first node
Msat_IntVecPush( pMan->vVarsInt, pOld->Num );
Msat_IntVecWriteEntry( pMan->vVarsUsed, pOld->Num, 1 );
pOld->TravId = pMan->nTravIds;
// add the second node
Msat_IntVecPush( pMan->vVarsInt, pNew->Num );
Msat_IntVecWriteEntry( pMan->vVarsUsed, pNew->Num, 1 );
pNew->TravId = pMan->nTravIds;
// create the variable order
for ( i = 0; i < Msat_IntVecReadSize(pMan->vVarsInt); i++ )
{
// get the new node on the frontier
Number = Msat_IntVecReadEntry(pMan->vVarsInt, i);
pNode = pMan->vNodes->pArray[Number];
if ( !Fraig_NodeIsAnd(pNode) )
continue;
// if the node does not have fanins, create them
if ( pNode->vFanins == NULL )
{
// create the fanins of the supergate
assert( pNode->fClauses == 0 );
// detecting a fanout-free cone (experiment only)
// Fraig_DetectFanoutFreeCone( pMan, pNode );
if ( fUseMuxes && Fraig_NodeIsMuxType(pNode) )
{
pNode->vFanins = Fraig_NodeVecAlloc( 4 );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p1)->p1) );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p1)->p2) );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p2)->p1) );
Fraig_NodeVecPushUnique( pNode->vFanins, Fraig_Regular(Fraig_Regular(pNode->p2)->p2) );
Fraig_SupergateAddClausesMux( pMan, pNode );
// Fraig_DetectFanoutFreeConeMux( pMan, pNode );
nMuxes++;
}
else
{
pNode->vFanins = Fraig_CollectSupergate( pNode, fUseMuxes );
Fraig_SupergateAddClauses( pMan, pNode, pNode->vFanins );
}
assert( pNode->vFanins->nSize > 1 );
pNode->fClauses = 1;
pMan->nVarsClauses++;
pNode->fMark2 = 1; // goes together with Fraig_SetupAdjacentMark()
}
// explore the implication fanins of pNode
for ( k = 0; k < pNode->vFanins->nSize; k++ )
{
pFanin = Fraig_Regular(pNode->vFanins->pArray[k]);
if ( pFanin->TravId == pMan->nTravIds ) // already collected
continue;
// collect and mark
Msat_IntVecPush( pMan->vVarsInt, pFanin->Num );
Msat_IntVecWriteEntry( pMan->vVarsUsed, pFanin->Num, 1 );
pFanin->TravId = pMan->nTravIds;
}
}
// set up the adjacent variable information
// Fraig_SetupAdjacent( pMan, pMan->vVarsInt );
Fraig_SetupAdjacentMark( pMan, pMan->vVarsInt );
}
ABC_NAMESPACE_IMPL_START
#ifdef FRAIG_ENABLE_FANOUTS
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Add the fanout to the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_NodeAddFaninFanout( Fraig_Node_t * pFanin, Fraig_Node_t * pFanout )
{
Fraig_Node_t * pPivot;
// pFanins is a fanin of pFanout
assert( !Fraig_IsComplement(pFanin) );
assert( !Fraig_IsComplement(pFanout) );
assert( Fraig_Regular(pFanout->p1) == pFanin || Fraig_Regular(pFanout->p2) == pFanin );
pPivot = pFanin->pFanPivot;
if ( pPivot == NULL )
{
pFanin->pFanPivot = pFanout;
return;
}
if ( Fraig_Regular(pPivot->p1) == pFanin )
{
if ( Fraig_Regular(pFanout->p1) == pFanin )
{
pFanout->pFanFanin1 = pPivot->pFanFanin1;
pPivot->pFanFanin1 = pFanout;
}
else // if ( Fraig_Regular(pFanout->p2) == pFanin )
{
pFanout->pFanFanin2 = pPivot->pFanFanin1;
pPivot->pFanFanin1 = pFanout;
}
}
else // if ( Fraig_Regular(pPivot->p2) == pFanin )
{
assert( Fraig_Regular(pPivot->p2) == pFanin );
if ( Fraig_Regular(pFanout->p1) == pFanin )
{
pFanout->pFanFanin1 = pPivot->pFanFanin2;
pPivot->pFanFanin2 = pFanout;
}
else // if ( Fraig_Regular(pFanout->p2) == pFanin )
{
pFanout->pFanFanin2 = pPivot->pFanFanin2;
pPivot->pFanFanin2 = pFanout;
}
}
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Adds choice nodes based on associativity.]
Description [Make nLimit big AND gates and add all decompositions
to the Fraig.]
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_ManAddChoices( Fraig_Man_t * pMan, int fVerbose, int nLimit )
{
// ProgressBar * pProgress;
char Buffer[100];
clock_t clkTotal = clock();
int i, nNodesBefore, nNodesAfter, nInputs, nMaxNodes;
int /*nMaxLevel,*/ nDistributive;
Fraig_Node_t *pNode, *pRepr;
Fraig_Node_t *pX, *pA, *pB, *pC, /* *pD,*/ *pN, /* *pQ, *pR,*/ *pT;
int fShortCut = 0;
nDistributive = 0;
// Fraig_ManSetApprox( pMan, 1 );
// NO functional reduction
if (fShortCut) Fraig_ManSetFuncRed( pMan, 0 );
// First we mark critical functions i.e. compute those
// nodes which lie on the critical path. Note that this
// doesn't update the required times on any choice nodes
// which are not the representatives
/*
nMaxLevel = Fraig_GetMaxLevel( pMan );
for ( i = 0; i < pMan->nOutputs; i++ )
{
Fraig_SetNodeRequired( pMan, pMan->pOutputs[i], nMaxLevel );
}
*/
nNodesBefore = Fraig_ManReadNodeNum( pMan );
nInputs = Fraig_ManReadInputNum( pMan );
nMaxNodes = nInputs + nLimit * ( nNodesBefore - nInputs );
printf ("Limit = %d, Before = %d\n", nMaxNodes, nNodesBefore );
if (0)
{
char buffer[128];
sprintf (buffer, "test" );
// Fraig_MappingShow( pMan, buffer );
}
// pProgress = Extra_ProgressBarStart( stdout, nMaxNodes );
Fraig_ManCheckConsistency( pMan );
for ( i = nInputs+1; (i < Fraig_ManReadNodeNum( pMan ))
&& (nMaxNodes > Fraig_ManReadNodeNum( pMan )); ++i )
{
// if ( i == nNodesBefore )
// break;
pNode = Fraig_ManReadIthNode( pMan, i );
assert ( pNode );
pRepr = pNode->pRepr ? pNode->pRepr : pNode;
//printf ("Slack: %d\n", Fraig_NodeReadSlack( pRepr ));
// All the new associative choices we add will have huge slack
// since we do not redo timing, and timing doesnt handle choices
// well anyway. However every newly added node is a choice of an
// existing critical node, so they are considered critical.
// if ( (Fraig_NodeReadSlack( pRepr ) > 3) && (i < nNodesBefore) )
// continue;
// if ( pNode->pRepr )
// continue;
// Try ((ab)c), x = ab -> (a(bc)) and (b(ac))
pX = Fraig_NodeReadOne(pNode);
pC = Fraig_NodeReadTwo(pNode);
if (Fraig_NodeIsAnd(pX) && !Fraig_IsComplement(pX))
{
pA = Fraig_NodeReadOne(Fraig_Regular(pX));
pB = Fraig_NodeReadTwo(Fraig_Regular(pX));
// pA = Fraig_NodeGetRepr( pA );
// pB = Fraig_NodeGetRepr( pB );
// pC = Fraig_NodeGetRepr( pC );
if (fShortCut)
{
pT = Fraig_NodeAnd(pMan, pB, pC);
if ( !pT->pRepr )
{
pN = Fraig_NodeAnd(pMan, pA, pT);
// Fraig_NodeAddChoice( pMan, pNode, pN );
}
}
else
pN = Fraig_NodeAnd(pMan, pA, Fraig_NodeAnd(pMan, pB, pC));
// assert ( Fraig_NodesEqual(pN, pNode) );
if (fShortCut)
{
pT = Fraig_NodeAnd(pMan, pA, pC);
if ( !pT->pRepr )
{
pN = Fraig_NodeAnd(pMan, pB, pT);
// Fraig_NodeAddChoice( pMan, pNode, pN );
}
}
else
pN = Fraig_NodeAnd(pMan, pB, Fraig_NodeAnd(pMan, pA, pC));
// assert ( Fraig_NodesEqual(pN, pNode) );
}
// Try (a(bc)), x = bc -> ((ab)c) and ((ac)b)
pA = Fraig_NodeReadOne(pNode);
pX = Fraig_NodeReadTwo(pNode);
if (Fraig_NodeIsAnd(pX) && !Fraig_IsComplement(pX))
{
pB = Fraig_NodeReadOne(Fraig_Regular(pX));
pC = Fraig_NodeReadTwo(Fraig_Regular(pX));
// pA = Fraig_NodeGetRepr( pA );
// pB = Fraig_NodeGetRepr( pB );
// pC = Fraig_NodeGetRepr( pC );
if (fShortCut)
{
pT = Fraig_NodeAnd(pMan, pA, pB);
if ( !pT->pRepr )
{
pN = Fraig_NodeAnd(pMan, pC, pT);
// Fraig_NodeAddChoice( pMan, pNode, pN );
}
}
else
pN = Fraig_NodeAnd(pMan, Fraig_NodeAnd(pMan, pA, pB), pC);
// assert ( Fraig_NodesEqual(pN, pNode) );
if (fShortCut)
{
pT = Fraig_NodeAnd(pMan, pA, pC);
if ( !pT->pRepr )
{
pN = Fraig_NodeAnd(pMan, pB, pT);
// Fraig_NodeAddChoice( pMan, pNode, pN );
}
}
else
pN = Fraig_NodeAnd(pMan, Fraig_NodeAnd(pMan, pA, pC), pB);
// assert ( Fraig_NodesEqual(pN, pNode) );
}
/*
// Try distributive transform
pQ = Fraig_NodeReadOne(pNode);
pR = Fraig_NodeReadTwo(pNode);
if ( (Fraig_IsComplement(pQ) && Fraig_NodeIsAnd(pQ))
&& (Fraig_IsComplement(pR) && Fraig_NodeIsAnd(pR)) )
{
pA = Fraig_NodeReadOne(Fraig_Regular(pQ));
pB = Fraig_NodeReadTwo(Fraig_Regular(pQ));
pC = Fraig_NodeReadOne(Fraig_Regular(pR));
pD = Fraig_NodeReadTwo(Fraig_Regular(pR));
// Now detect the !(xy + xz) pattern, store
// x in pA, y in pB and z in pC and set pD = 0 to indicate
// pattern was found
assert (pD != 0);
if (pA == pC) { pC = pD; pD = 0; }
if (pA == pD) { pD = 0; }
if (pB == pC) { pB = pA; pA = pC; pC = pD; pD = 0; }
if (pB == pD) { pB = pA; pA = pD; pD = 0; }
if (pD == 0)
{
nDistributive++;
pN = Fraig_Not(Fraig_NodeAnd(pMan, pA,
Fraig_NodeOr(pMan, pB, pC)));
if (fShortCut) Fraig_NodeAddChoice( pMan, pNode, pN );
// assert ( Fraig_NodesEqual(pN, pNode) );
}
}
*/
if ( i % 1000 == 0 )
{
sprintf( Buffer, "Adding choice %6d...", i - nNodesBefore );
// Extra_ProgressBarUpdate( pProgress, i, Buffer );
}
}
// Extra_ProgressBarStop( pProgress );
Fraig_ManCheckConsistency( pMan );
nNodesAfter = Fraig_ManReadNodeNum( pMan );
printf ( "Nodes before = %6d. Nodes with associative choices = %6d. Increase = %4.2f %%.\n",
nNodesBefore, nNodesAfter, ((float)(nNodesAfter - nNodesBefore)) * 100.0/(nNodesBefore - nInputs) );
printf ( "Distributive = %d\n", nDistributive );
}
/**Function*************************************************************
Synopsis [Recognizes what nodes are control and data inputs of a MUX.]
Description [If the node is a MUX, returns the control variable C.
Assigns nodes T and E to be the then and else variables of the MUX.
Node C is never complemented. Nodes T and E can be complemented.
This function also recognizes EXOR/NEXOR gates as MUXes.]
SideEffects []
SeeAlso []
***********************************************************************/
Fraig_Node_t * Fraig_NodeRecognizeMux( Fraig_Node_t * pNode, Fraig_Node_t ** ppNodeT, Fraig_Node_t ** ppNodeE )
{
Fraig_Node_t * pNode1, * pNode2;
assert( !Fraig_IsComplement(pNode) );
assert( Fraig_NodeIsMuxType(pNode) );
// get children
pNode1 = Fraig_Regular(pNode->p1);
pNode2 = Fraig_Regular(pNode->p2);
// find the control variable
if ( pNode1->p1 == Fraig_Not(pNode2->p1) )
{
if ( Fraig_IsComplement(pNode1->p1) )
{ // pNode2->p1 is positive phase of C
*ppNodeT = Fraig_Not(pNode2->p2);
*ppNodeE = Fraig_Not(pNode1->p2);
return pNode2->p1;
}
else
{ // pNode1->p1 is positive phase of C
*ppNodeT = Fraig_Not(pNode1->p2);
*ppNodeE = Fraig_Not(pNode2->p2);
return pNode1->p1;
}
}
else if ( pNode1->p1 == Fraig_Not(pNode2->p2) )
{
if ( Fraig_IsComplement(pNode1->p1) )
{ // pNode2->p2 is positive phase of C
*ppNodeT = Fraig_Not(pNode2->p1);
*ppNodeE = Fraig_Not(pNode1->p2);
return pNode2->p2;
}
else
{ // pNode1->p1 is positive phase of C
*ppNodeT = Fraig_Not(pNode1->p2);
*ppNodeE = Fraig_Not(pNode2->p1);
return pNode1->p1;
}
}
else if ( pNode1->p2 == Fraig_Not(pNode2->p1) )
{
if ( Fraig_IsComplement(pNode1->p2) )
{ // pNode2->p1 is positive phase of C
*ppNodeT = Fraig_Not(pNode2->p2);
*ppNodeE = Fraig_Not(pNode1->p1);
return pNode2->p1;
}
else
{ // pNode1->p2 is positive phase of C
*ppNodeT = Fraig_Not(pNode1->p1);
*ppNodeE = Fraig_Not(pNode2->p2);
return pNode1->p2;
}
}
else if ( pNode1->p2 == Fraig_Not(pNode2->p2) )
{
if ( Fraig_IsComplement(pNode1->p2) )
{ // pNode2->p2 is positive phase of C
*ppNodeT = Fraig_Not(pNode2->p1);
*ppNodeE = Fraig_Not(pNode1->p1);
return pNode2->p2;
}
else
{ // pNode1->p2 is positive phase of C
*ppNodeT = Fraig_Not(pNode1->p1);
*ppNodeE = Fraig_Not(pNode2->p1);
return pNode1->p2;
}
}
assert( 0 ); // this is not MUX
return NULL;
}
Fraig_Node_t * Fraig_NodeReadTwo( Fraig_Node_t * p ) { assert (!Fraig_IsComplement(p)); return p->p2; }
/**Function*************************************************************
Synopsis [The internal AND operation for the two FRAIG nodes.]
Description [This procedure is the core of the FRAIG package, because
it performs the two-step canonicization of FRAIG nodes. The first step
involves the lookup in the structural hash table (which hashes two ANDs
into a node that has them as fanins, if such a node exists). If the node
is not found in the structural hash table, an attempt is made to find a
functionally equivalent node in another hash table (which hashes the
simulation info into the nodes, which has this simulation info). Some
tricks used on the way are described in the comments to the code and
in the paper "FRAIGs: Functionally reduced AND-INV graphs".]
SideEffects []
SeeAlso []
***********************************************************************/
Fraig_Node_t * Fraig_NodeAndCanon( Fraig_Man_t * pMan, Fraig_Node_t * p1, Fraig_Node_t * p2 )
{
Fraig_Node_t * pNodeNew, * pNodeOld, * pNodeRepr;
int fUseSatCheck;
// int RetValue;
// check for trivial cases
if ( p1 == p2 )
return p1;
if ( p1 == Fraig_Not(p2) )
return Fraig_Not(pMan->pConst1);
if ( Fraig_NodeIsConst(p1) )
{
if ( p1 == pMan->pConst1 )
return p2;
return Fraig_Not(pMan->pConst1);
}
if ( Fraig_NodeIsConst(p2) )
{
if ( p2 == pMan->pConst1 )
return p1;
return Fraig_Not(pMan->pConst1);
}
/*
// check for less trivial cases
if ( Fraig_IsComplement(p1) )
{
if ( RetValue = Fraig_NodeIsInSupergate( Fraig_Regular(p1), p2 ) )
{
if ( RetValue == -1 )
pMan->nImplies0++;
else
pMan->nImplies1++;
if ( RetValue == -1 )
return p2;
}
}
else
{
if ( RetValue = Fraig_NodeIsInSupergate( p1, p2 ) )
{
if ( RetValue == 1 )
pMan->nSimplifies1++;
else
pMan->nSimplifies0++;
if ( RetValue == 1 )
return p1;
return Fraig_Not(pMan->pConst1);
}
}
if ( Fraig_IsComplement(p2) )
{
if ( RetValue = Fraig_NodeIsInSupergate( Fraig_Regular(p2), p1 ) )
{
if ( RetValue == -1 )
pMan->nImplies0++;
else
pMan->nImplies1++;
if ( RetValue == -1 )
return p1;
}
}
else
{
if ( RetValue = Fraig_NodeIsInSupergate( p2, p1 ) )
{
if ( RetValue == 1 )
pMan->nSimplifies1++;
else
pMan->nSimplifies0++;
if ( RetValue == 1 )
return p2;
return Fraig_Not(pMan->pConst1);
}
}
*/
// perform level-one structural hashing
if ( Fraig_HashTableLookupS( pMan, p1, p2, &pNodeNew ) ) // the node with these children is found
{
// if the existent node is part of the cone of unused logic
// (that is logic feeding the node which is equivalent to the given node)
// return the canonical representative of this node
// determine the phase of the given node, with respect to its canonical form
pNodeRepr = Fraig_Regular(pNodeNew)->pRepr;
if ( pMan->fFuncRed && pNodeRepr )
return Fraig_NotCond( pNodeRepr, Fraig_IsComplement(pNodeNew) ^ Fraig_NodeComparePhase(Fraig_Regular(pNodeNew), pNodeRepr) );
// otherwise, the node is itself a canonical representative, return it
return pNodeNew;
}
// the same node is not found, but the new one is created
// if one level hashing is requested (without functionality hashing), return
if ( !pMan->fFuncRed )
return pNodeNew;
// check if the new node is unique using the simulation info
if ( pNodeNew->nOnes == 0 || pNodeNew->nOnes == (unsigned)pMan->nWordsRand * 32 )
{
pMan->nSatZeros++;
if ( !pMan->fDoSparse ) // if we do not do sparse functions, skip
return pNodeNew;
// check the sparse function simulation hash table
pNodeOld = Fraig_HashTableLookupF0( pMan, pNodeNew );
if ( pNodeOld == NULL ) // the node is unique (it is added to the table)
return pNodeNew;
}
else
{
// check the simulation hash table
pNodeOld = Fraig_HashTableLookupF( pMan, pNodeNew );
if ( pNodeOld == NULL ) // the node is unique
return pNodeNew;
}
assert( pNodeOld->pRepr == 0 );
// there is another node which looks the same according to simulation
// use SAT to resolve the ambiguity
fUseSatCheck = (pMan->nInspLimit == 0 || Fraig_ManReadInspects(pMan) < pMan->nInspLimit);
if ( fUseSatCheck && Fraig_NodeIsEquivalent( pMan, pNodeOld, pNodeNew, pMan->nBTLimit, 1000000 ) )
{
// set the node to be equivalent with this node
// to prevent loops, only set if the old node is not in the TFI of the new node
// the loop may happen in the following case: suppose
// NodeC = AND(NodeA, NodeB) and at the same time NodeA => NodeB
// in this case, NodeA and NodeC are functionally equivalent
// however, NodeA is a fanin of node NodeC (this leads to the loop)
// add the node to the list of equivalent nodes or dereference it
if ( pMan->fChoicing && !Fraig_CheckTfi( pMan, pNodeOld, pNodeNew ) )
{
// if the old node is not in the TFI of the new node and choicing
// is enabled, add the new node to the list of equivalent ones
pNodeNew->pNextE = pNodeOld->pNextE;
pNodeOld->pNextE = pNodeNew;
}
// set the canonical representative of this node
pNodeNew->pRepr = pNodeOld;
// return the equivalent node
return Fraig_NotCond( pNodeOld, Fraig_NodeComparePhase(pNodeOld, pNodeNew) );
}
// now we add another member to this simulation class
if ( pNodeNew->nOnes == 0 || pNodeNew->nOnes == (unsigned)pMan->nWordsRand * 32 )
{
Fraig_Node_t * pNodeTemp;
assert( pMan->fDoSparse );
pNodeTemp = Fraig_HashTableLookupF0( pMan, pNodeNew );
// assert( pNodeTemp == NULL );
// Fraig_HashTableInsertF0( pMan, pNodeNew );
}
else
{
pNodeNew->pNextD = pNodeOld->pNextD;
pNodeOld->pNextD = pNodeNew;
}
// return the new node
assert( pNodeNew->pRepr == 0 );
return pNodeNew;
}
/**Function*************************************************************
Synopsis [Prepares the SAT solver to run on the two nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_ManCheckClauseUsingSat( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2, int nBTLimit )
{
Fraig_Node_t * pNode1R, * pNode2R;
int RetValue, RetValue1, i, clk;
int fVerbose = 0;
pNode1R = Fraig_Regular(pNode1);
pNode2R = Fraig_Regular(pNode2);
assert( pNode1R != pNode2R );
// make sure the solver is allocated and has enough variables
if ( p->pSat == NULL )
Fraig_ManCreateSolver( p );
// make sure the SAT solver has enough variables
for ( i = Msat_SolverReadVarNum(p->pSat); i < p->vNodes->nSize; i++ )
Msat_SolverAddVar( p->pSat, p->vNodes->pArray[i]->Level );
// get the logic cone
clk = clock();
Fraig_OrderVariables( p, pNode1R, pNode2R );
// Fraig_PrepareCones( p, pNode1R, pNode2R );
p->timeTrav += clock() - clk;
////////////////////////////////////////////
// prepare the solver to run incrementally on these variables
//clk = clock();
Msat_SolverPrepare( p->pSat, p->vVarsInt );
//p->time3 += clock() - clk;
// solve under assumptions
// A = 1; B = 0 OR A = 1; B = 1
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1R->Num, !Fraig_IsComplement(pNode1)) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2R->Num, !Fraig_IsComplement(pNode2)) );
// run the solver
clk = clock();
RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, 1000000 );
p->timeSat += clock() - clk;
if ( RetValue1 == MSAT_FALSE )
{
//p->time1 += clock() - clk;
if ( fVerbose )
{
printf( "unsat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// add the clause
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1R->Num, Fraig_IsComplement(pNode1)) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2R->Num, Fraig_IsComplement(pNode2)) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
// p->nSatProofImp++;
return 1;
}
else if ( RetValue1 == MSAT_TRUE )
{
//p->time2 += clock() - clk;
if ( fVerbose )
{
printf( "sat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// record the counter example
// Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pNode1R, pNode2R );
p->nSatCounterImp++;
return 0;
}
else // if ( RetValue1 == MSAT_UNKNOWN )
{
p->time3 += clock() - clk;
p->nSatFailsImp++;
return 0;
}
}
/**Function*************************************************************
Synopsis [Adds clauses to the solver.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_SupergateAddClausesMux( Fraig_Man_t * p, Fraig_Node_t * pNode )
{
Fraig_Node_t * pNodeI, * pNodeT, * pNodeE;
int RetValue, VarF, VarI, VarT, VarE, fCompT, fCompE;
assert( !Fraig_IsComplement( pNode ) );
assert( Fraig_NodeIsMuxType( pNode ) );
// get nodes (I = if, T = then, E = else)
pNodeI = Fraig_NodeRecognizeMux( pNode, &pNodeT, &pNodeE );
// get the variable numbers
VarF = pNode->Num;
VarI = pNodeI->Num;
VarT = Fraig_Regular(pNodeT)->Num;
VarE = Fraig_Regular(pNodeE)->Num;
// get the complementation flags
fCompT = Fraig_IsComplement(pNodeT);
fCompE = Fraig_IsComplement(pNodeE);
// f = ITE(i, t, e)
// i' + t' + f
// i' + t + f'
// i + e' + f
// i + e + f'
// create four clauses
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarI, 1) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarT, 1^fCompT) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarF, 0) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarI, 1) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarT, 0^fCompT) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarF, 1) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarI, 0) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarE, 1^fCompE) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarF, 0) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarI, 0) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarE, 0^fCompE) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarF, 1) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
// two additional clauses
// t' & e' -> f'
// t & e -> f
// t + e + f'
// t' + e' + f
if ( VarT == VarE )
{
// assert( fCompT == !fCompE );
return;
}
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarT, 0^fCompT) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarE, 0^fCompE) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarF, 1) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarT, 1^fCompT) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarE, 1^fCompE) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(VarF, 0) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
}
/**Function*************************************************************
Synopsis [Checks whether two nodes are functinally equivalent.]
Description [The flag (fComp) tells whether the nodes to be checked
are in the opposite polarity. The second flag (fSkipZeros) tells whether
the checking should be performed if the simulation vectors are zeros.
Returns 1 if the nodes are equivalent; 0 othewise.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew, int nBTLimit, int nTimeLimit )
{
int RetValue, RetValue1, i, fComp, clk;
int fVerbose = 0;
int fSwitch = 0;
// make sure the nodes are not complemented
assert( !Fraig_IsComplement(pNew) );
assert( !Fraig_IsComplement(pOld) );
assert( pNew != pOld );
// if at least one of the nodes is a failed node, perform adjustments:
// if the backtrack limit is small, simply skip this node
// if the backtrack limit is > 10, take the quare root of the limit
if ( nBTLimit > 0 && (pOld->fFailTfo || pNew->fFailTfo) )
{
p->nSatFails++;
// return 0;
// if ( nBTLimit > 10 )
// nBTLimit /= 10;
if ( nBTLimit <= 10 )
return 0;
nBTLimit = (int)sqrt(nBTLimit);
// fSwitch = 1;
}
p->nSatCalls++;
// make sure the solver is allocated and has enough variables
if ( p->pSat == NULL )
Fraig_ManCreateSolver( p );
// make sure the SAT solver has enough variables
for ( i = Msat_SolverReadVarNum(p->pSat); i < p->vNodes->nSize; i++ )
Msat_SolverAddVar( p->pSat, p->vNodes->pArray[i]->Level );
/*
{
Fraig_Node_t * ppNodes[2] = { pOld, pNew };
extern void Fraig_MappingShowNodes( Fraig_Man_t * pMan, Fraig_Node_t ** ppRoots, int nRoots, char * pFileName );
Fraig_MappingShowNodes( p, ppNodes, 2, "temp_aig" );
}
*/
nMuxes = 0;
// get the logic cone
clk = clock();
// Fraig_VarsStudy( p, pOld, pNew );
Fraig_OrderVariables( p, pOld, pNew );
// Fraig_PrepareCones( p, pOld, pNew );
p->timeTrav += clock() - clk;
// printf( "The number of MUXes detected = %d (%5.2f %% of logic). ", nMuxes, 300.0*nMuxes/(p->vNodes->nSize - p->vInputs->nSize) );
// PRT( "Time", clock() - clk );
if ( fVerbose )
printf( "%d(%d) - ", Fraig_CountPis(p,p->vVarsInt), Msat_IntVecReadSize(p->vVarsInt) );
// prepare variable activity
Fraig_SetActivity( p, pOld, pNew );
// get the complemented attribute
fComp = Fraig_NodeComparePhase( pOld, pNew );
//Msat_SolverPrintClauses( p->pSat );
////////////////////////////////////////////
// prepare the solver to run incrementally on these variables
//clk = clock();
Msat_SolverPrepare( p->pSat, p->vVarsInt );
//p->time3 += clock() - clk;
// solve under assumptions
// A = 1; B = 0 OR A = 1; B = 1
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 0) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, !fComp) );
//Msat_SolverWriteDimacs( p->pSat, "temp_fraig.cnf" );
// run the solver
clk = clock();
RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, nTimeLimit );
p->timeSat += clock() - clk;
if ( RetValue1 == MSAT_FALSE )
{
//p->time1 += clock() - clk;
if ( fVerbose )
{
printf( "unsat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// add the clause
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 1) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
// continue solving the other implication
}
else if ( RetValue1 == MSAT_TRUE )
{
//p->time2 += clock() - clk;
if ( fVerbose )
{
printf( "sat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// record the counter example
Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pOld, pNew );
// if ( pOld->fFailTfo || pNew->fFailTfo )
// printf( "*" );
// printf( "s(%d)", pNew->Level );
if ( fSwitch )
printf( "s(%d)", pNew->Level );
p->nSatCounter++;
return 0;
}
else // if ( RetValue1 == MSAT_UNKNOWN )
{
p->time3 += clock() - clk;
// if ( pOld->fFailTfo || pNew->fFailTfo )
// printf( "*" );
// printf( "T(%d)", pNew->Level );
// mark the node as the failed node
if ( pOld != p->pConst1 )
pOld->fFailTfo = 1;
pNew->fFailTfo = 1;
// p->nSatFails++;
if ( fSwitch )
printf( "T(%d)", pNew->Level );
p->nSatFailsReal++;
return 0;
}
// if the old node was constant 0, we already know the answer
if ( pOld == p->pConst1 )
return 1;
////////////////////////////////////////////
// prepare the solver to run incrementally
//clk = clock();
Msat_SolverPrepare( p->pSat, p->vVarsInt );
//p->time3 += clock() - clk;
// solve under assumptions
// A = 0; B = 1 OR A = 0; B = 0
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 1) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, fComp) );
// run the solver
clk = clock();
RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, nTimeLimit );
p->timeSat += clock() - clk;
if ( RetValue1 == MSAT_FALSE )
{
//p->time1 += clock() - clk;
if ( fVerbose )
{
printf( "unsat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// add the clause
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 0) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, !fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
// continue solving the other implication
}
else if ( RetValue1 == MSAT_TRUE )
{
//p->time2 += clock() - clk;
if ( fVerbose )
{
printf( "sat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// record the counter example
Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pOld, pNew );
p->nSatCounter++;
// if ( pOld->fFailTfo || pNew->fFailTfo )
// printf( "*" );
// printf( "s(%d)", pNew->Level );
if ( fSwitch )
printf( "s(%d)", pNew->Level );
return 0;
}
else // if ( RetValue1 == MSAT_UNKNOWN )
{
p->time3 += clock() - clk;
// if ( pOld->fFailTfo || pNew->fFailTfo )
// printf( "*" );
// printf( "T(%d)", pNew->Level );
if ( fSwitch )
printf( "T(%d)", pNew->Level );
// mark the node as the failed node
pOld->fFailTfo = 1;
pNew->fFailTfo = 1;
// p->nSatFails++;
p->nSatFailsReal++;
return 0;
}
// return SAT proof
p->nSatProof++;
// if ( pOld->fFailTfo || pNew->fFailTfo )
// printf( "*" );
// printf( "u(%d)", pNew->Level );
if ( fSwitch )
printf( "u(%d)", pNew->Level );
return 1;
}
/**Function*************************************************************
Synopsis [Checks whether pOld => pNew.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_NodeIsImplication( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew, int nBTLimit )
{
int RetValue, RetValue1, i, fComp, clk;
int fVerbose = 0;
// make sure the nodes are not complemented
assert( !Fraig_IsComplement(pNew) );
assert( !Fraig_IsComplement(pOld) );
assert( pNew != pOld );
p->nSatCallsImp++;
// make sure the solver is allocated and has enough variables
if ( p->pSat == NULL )
Fraig_ManCreateSolver( p );
// make sure the SAT solver has enough variables
for ( i = Msat_SolverReadVarNum(p->pSat); i < p->vNodes->nSize; i++ )
Msat_SolverAddVar( p->pSat, p->vNodes->pArray[i]->Level );
// get the logic cone
clk = clock();
Fraig_OrderVariables( p, pOld, pNew );
// Fraig_PrepareCones( p, pOld, pNew );
p->timeTrav += clock() - clk;
if ( fVerbose )
printf( "%d(%d) - ", Fraig_CountPis(p,p->vVarsInt), Msat_IntVecReadSize(p->vVarsInt) );
// get the complemented attribute
fComp = Fraig_NodeComparePhase( pOld, pNew );
//Msat_SolverPrintClauses( p->pSat );
////////////////////////////////////////////
// prepare the solver to run incrementally on these variables
//clk = clock();
Msat_SolverPrepare( p->pSat, p->vVarsInt );
//p->time3 += clock() - clk;
// solve under assumptions
// A = 1; B = 0 OR A = 1; B = 1
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 0) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, !fComp) );
// run the solver
clk = clock();
RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, 1000000 );
p->timeSat += clock() - clk;
if ( RetValue1 == MSAT_FALSE )
{
//p->time1 += clock() - clk;
if ( fVerbose )
{
printf( "unsat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// add the clause
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 1) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, fComp) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
// p->nSatProofImp++;
return 1;
}
else if ( RetValue1 == MSAT_TRUE )
{
//p->time2 += clock() - clk;
if ( fVerbose )
{
printf( "sat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// record the counter example
Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pOld, pNew );
p->nSatCounterImp++;
return 0;
}
else // if ( RetValue1 == MSAT_UNKNOWN )
{
p->time3 += clock() - clk;
p->nSatFailsImp++;
return 0;
}
}
/**Function*************************************************************
Synopsis [Simulates the node.]
Description [Simulates the random or dynamic simulation info through
the node. Uses phases of the children to determine their real simulation
info. Uses phase of the node to determine the way its simulation info
is stored. The resulting info is guaranteed to be 0 for the first pattern.]
SideEffects [This procedure modified the hash value of the simulation info.]
SeeAlso []
***********************************************************************/
void Fraig_NodeSimulate( Fraig_Node_t * pNode, int iWordStart, int iWordStop, int fUseRand )
{
unsigned * pSims, * pSims1, * pSims2;
unsigned uHash;
int fCompl, fCompl1, fCompl2, i;
assert( !Fraig_IsComplement(pNode) );
// get hold of the simulation information
pSims = fUseRand? pNode->puSimR : pNode->puSimD;
pSims1 = fUseRand? Fraig_Regular(pNode->p1)->puSimR : Fraig_Regular(pNode->p1)->puSimD;
pSims2 = fUseRand? Fraig_Regular(pNode->p2)->puSimR : Fraig_Regular(pNode->p2)->puSimD;
// get complemented attributes of the children using their random info
fCompl = pNode->fInv;
fCompl1 = Fraig_NodeIsSimComplement(pNode->p1);
fCompl2 = Fraig_NodeIsSimComplement(pNode->p2);
// simulate
uHash = 0;
if ( fCompl1 && fCompl2 )
{
if ( fCompl )
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = (pSims1[i] | pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
else
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = ~(pSims1[i] | pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
}
else if ( fCompl1 && !fCompl2 )
{
if ( fCompl )
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = (pSims1[i] | ~pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
else
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = (~pSims1[i] & pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
}
else if ( !fCompl1 && fCompl2 )
{
if ( fCompl )
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = (~pSims1[i] | pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
else
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = (pSims1[i] & ~pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
}
else // if ( !fCompl1 && !fCompl2 )
{
if ( fCompl )
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = ~(pSims1[i] & pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
else
for ( i = iWordStart; i < iWordStop; i++ )
{
pSims[i] = (pSims1[i] & pSims2[i]);
uHash ^= pSims[i] * s_FraigPrimes[i];
}
}
if ( fUseRand )
pNode->uHashR ^= uHash;
else
pNode->uHashD ^= uHash;
}
Fraig_Node_t * Fraig_NodeReadOne( Fraig_Node_t * p ) { assert (!Fraig_IsComplement(p)); return p->p1; }
